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SN74LS373DWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS373DWR

Texas Instruments · Latches · SOIC-20-300mil

SN74LS373DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OC input Buffered active-low output control; when low the eight 3-state outputs are enabled, and when high they are placed in the high-impedance state without affecting the internal latch operation.
2 1Q tri_state Latch 1 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
3 1D input Data input for latch 1; while C is high the Q output follows D, and the level present when C goes low is latched.
4 2D input Data input for latch 2; while C is high the Q output follows D, and the level present when C goes low is latched.
5 2Q tri_state Latch 2 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
6 3Q tri_state Latch 3 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
7 3D input Data input for latch 3; while C is high the Q output follows D, and the level present when C goes low is latched.
8 4D input Data input for latch 4; while C is high the Q output follows D, and the level present when C goes low is latched.
9 4Q tri_state Latch 4 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
10 GND power_in Ground reference for the device.
11 C input Latch enable input for the ’LS373; the Q outputs follow D while C is high and hold the data when C goes low.
12 5Q tri_state Latch 5 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
13 5D input Data input for latch 5; while C is high the Q output follows D, and the level present when C goes low is latched.
14 6D input Data input for latch 6; while C is high the Q output follows D, and the level present when C goes low is latched.
15 6Q tri_state Latch 6 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
16 7Q tri_state Latch 7 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
17 7D input Data input for latch 7; while C is high the Q output follows D, and the level present when C goes low is latched.
18 8D input Data input for latch 8; while C is high the Q output follows D, and the level present when C goes low is latched.
19 8Q tri_state Latch 8 bus-driving 3-state output that follows the latched data and goes high-impedance when OC is high.
20 VCC power_in Supply voltage pin; the datasheet text provided does not state its numeric limits.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LS373DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74ls373dwr-etched.step / sn74ls373dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls373dwr.step / sn74ls373dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 5d2c396010d2b304, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF