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SN74LS21DR

Public Made by Adom

by adom

Texas Instruments Gates, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn74ls21dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sn74ls21dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
README.md sn74ls21dr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sn74ls21dr-etched.fit.json sn74ls21dr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74ls21dr-etched.glb sn74ls21dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
sn74ls21dr-etched.step sn74ls21dr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
sn74ls21dr.glb Publish 0.1.0 · Ray
sn74ls21dr.kicad_mod Publish 0.1.0 · Ray
sn74ls21dr.kicad_sym Publish 0.1.0 · Ray
sn74ls21dr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sn74ls21dr.step Publish 0.1.0 · Ray

SN74LS21DR

Texas Instruments · Gates · SOIC-14

SN74LS21DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V. Input current IIH = 20 uA max at 2.7 V; IIL = -0.4 mA max at 0.4 V.
2 1B input Gate 1 input B. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
3 NC unconnected No internal connection. Leave floating or tie to a convenient net.
4 1C input Gate 1 input C. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
5 1D input Gate 1 input D. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
6 1Y output Gate 1 output. Y = 1A AND 1B AND 1C AND 1D (positive logic). LSTTL totem-pole output; VOH >= 2.7 V at IOH = -0.4 mA; VOL <= 0.5 V at IOL = 8 mA.
7 GND power_in Device ground reference (0 V).
8 2Y output Gate 2 output. Y = 2A AND 2B AND 2C AND 2D (positive logic). LSTTL totem-pole output; VOH >= 2.7 V at IOH = -0.4 mA; VOL <= 0.5 V at IOL = 8 mA.
9 2A input Gate 2 input A. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
10 2B input Gate 2 input B. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
11 NC unconnected No internal connection. Leave floating or tie to a convenient net.
12 2C input Gate 2 input C. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
13 2D input Gate 2 input D. LSTTL logic input; VIH >= 2 V, VIL <= 0.8 V.
14 VCC power_in Positive supply. Recommended 4.75-5.25 V (SN74LS21), absolute maximum 7 V. Typical ICCH = 1.2 mA, ICCL = 2.2 mA.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • SN74LS21DRD
  • SN74LS21DR
  • SN74LS21DRN
  • SN74LS21DRNE4
  • SN74LS21DRNSR
  • SN74LS21DRJ
  • SN74LS21DRW
  • SN74LS21DRFK

CAD (KiCad official)

  • Symbol: SN74LS21DR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ls21dr-etched.step / sn74ls21dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls21dr.step / sn74ls21dr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74ls21dr.step 195 KB You want the bare part, or you mark your own boards.
sn74ls21dr-etched.step 2.2 MB You want the part with SN74LS21DR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 566 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 de3373b5914eb45e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF