SN74LS01DR

{
  "slug": "sn74ls01dr",
  "version": "0.1.0",
  "type": "component",
  "description": "lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "sn74ls01dr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74ls01dr.kicad_sym",
    "sn74ls01dr.kicad_mod",
    "sn74ls01dr.glb",
    "sn74ls01dr.step",
    "sn74ls01dr.lbr",
    "docs/hero.png",
    "docs/sn74ls01dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74ls01dr-hero.glb",
    "sn74ls01dr-hero.overlay.json",
    "sn74ls01dr-etched.glb"
  ],
  "component": {
    "mpn": "SN74LS01DR",
    "manufacturer": "lingxingic",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603380566846676992",
    "parts": {
      "symbol": "sn74ls01dr.kicad_sym",
      "footprint": "sn74ls01dr.kicad_mod",
      "model_3d": "sn74ls01dr-hero.glb",
      "model_3d_plain": "sn74ls01dr-etched.glb",
      "model_3d_step": "sn74ls01dr-etched.step",
      "model_3d_step_plain": "sn74ls01dr.step",
      "lbr": "sn74ls01dr.lbr"
    },
    "distributor_links": {
      "lcsc": "C22449648"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T01:28:58Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1Y",
        "type": "output",
        "description": "Open-drain data output of gate 1, which goes low only when 1A and 1B are both high and is otherwise high-impedance (Z) per the function table."
      },
      {
        "number": "2",
        "name": "1A",
        "type": "input",
        "description": "Data input A of gate 1, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "3",
        "name": "1B",
        "type": "input",
        "description": "Data input B of gate 1, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "4",
        "name": "2Y",
        "type": "output",
        "description": "Open-drain data output of gate 2, which goes low only when 2A and 2B are both high and is otherwise high-impedance (Z) per the function table."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Data input A of gate 2, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Data input B of gate 2, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for all voltages in the datasheet."
      },
      {
        "number": "8",
        "name": "3A",
        "type": "input",
        "description": "Data input A of gate 3, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "9",
        "name": "3B",
        "type": "input",
        "description": "Data input B of gate 3, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "10",
        "name": "3Y",
        "type": "output",
        "description": "Open-drain data output of gate 3, which goes low only when 3A and 3B are both high and is otherwise high-impedance (Z) per the function table."
      },
      {
        "number": "11",
        "name": "4A",
        "type": "input",
        "description": "Data input A of gate 4, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "12",
        "name": "4B",
        "type": "input",
        "description": "Data input B of gate 4, with input voltage limited to 0 V to VCC and CMOS-level input thresholds."
      },
      {
        "number": "13",
        "name": "4Y",
        "type": "output",
        "description": "Open-drain data output of gate 4, which goes low only when 4A and 4B are both high and is otherwise high-impedance (Z) per the function table."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage with a recommended operating range of 2.0 V to 6.0 V (5.0 V typical)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package SOP14 is matched to the SN74LS01DR (LX) ordering entry on page 3 (reel packing, SOP14, 8.7 m; Marking inconsistency: page 3 gives marking code HC01 for SOP14 (and 74HC01 in the tube table, with ; Open-drain outputs are mapped to KiCad type 'output' because open_collector is not an allowed type i"
        ],
        "pages_sent": 14,
        "cost_usd": 0.0541,
        "at": "2026-10-21T01:26:10"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603380566846676992",
        "pages": 14,
        "sha256": "ff190778a023ec5f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "sn74ls01dr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74ls01dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "effb46d0a1143fba2a44951dc69bfce31c2904cd796bc9474051c52994f8b310",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}