component
SN74LS01DR
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS01DR
lingxingic · Logic Gates · SOP-14
SN74LS01DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Open-drain data output of gate 1, which goes low only when 1A and 1B are both high and is otherwise high-impedance (Z) per the function table. |
| 2 | 1A | input | Data input A of gate 1, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 3 | 1B | input | Data input B of gate 1, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 4 | 2Y | output | Open-drain data output of gate 2, which goes low only when 2A and 2B are both high and is otherwise high-impedance (Z) per the function table. |
| 5 | 2A | input | Data input A of gate 2, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 6 | 2B | input | Data input B of gate 2, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 7 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 8 | 3A | input | Data input A of gate 3, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 9 | 3B | input | Data input B of gate 3, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 10 | 3Y | output | Open-drain data output of gate 3, which goes low only when 3A and 3B are both high and is otherwise high-impedance (Z) per the function table. |
| 11 | 4A | input | Data input A of gate 4, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 12 | 4B | input | Data input B of gate 4, with input voltage limited to 0 V to VCC and CMOS-level input thresholds. |
| 13 | 4Y | output | Open-drain data output of gate 4, which goes low only when 4A and 4B are both high and is otherwise high-impedance (Z) per the function table. |
| 14 | VCC | power_in | Supply voltage with a recommended operating range of 2.0 V to 6.0 V (5.0 V typical). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| supply current | ICC | 50 | mA | 5 | |||
| ground current | IGND | -50 | mA | 5 | |||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 5 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 5 | |
| output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 5 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| soldering temperature | TL | 260 | ℃ | 10s, SOP/TSSOP | 5 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| input voltage | VI | 0 | V | 5 | |||
| output voltage | VO | 0 | V | 5 | |||
| ambient temperature | Tamb | -40 | 125 | ℃ | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V; Tamb=-40℃ to +85℃ | 6 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V; Tamb=-40℃ to +85℃ | 6 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +85℃ | 6 | |
| LOW-level output voltage | VOL | 0.16 | 0.33 | V | VCC=6.0V; IO=5.2mA; Tamb=-40℃ to +85℃ | 6 | |
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +85℃ | 6 | |
| OFF-state output current | IOZ | -5 | 5 | uA | VCC=6.0V; VI=VIH or VIL; VO=VCC or GND; Tamb=-40℃ to +85℃ | 6 | |
| supply current | ICC | 10 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +85℃ | 6 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC=2.0V; Tamb=-40℃ to +125℃ | 7 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC=4.5V; Tamb=-40℃ to +125℃ | 7 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC=6.0V; Tamb=-40℃ to +125℃ | 7 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC=2.0V; Tamb=-40℃ to +125℃ | 7 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC=4.5V; Tamb=-40℃ to +125℃ | 7 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC=6.0V; Tamb=-40℃ to +125℃ | 7 | ||
| LOW-level output voltage | VOL | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40℃ to +125℃ | 7 | ||
| LOW-level output voltage | VOL | 0.4 | V | VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +125℃ | 7 | ||
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +125℃ | 7 | |
| OFF-state output current | IOZ | -10 | 10 | uA | VCC=6.0V; VI=VIH or VIL; VO=VCC or GND; Tamb=-40℃ to +125℃ | 7 | |
| supply current | ICC | 160 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +125℃ | 7 | ||
| propagation delay | tPLZ, tPZL | 41 | 155 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ | 8 | |
| propagation delay | tPLZ, tPZL | 15 | 23 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ | 8 | |
| propagation delay | tPLZ, tPZL | 12 | 20 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ | 8 | |
| transition time | tTHL | 19 | 95 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ | 8 | |
| transition time | tTHL | 7 | 19 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ | 8 | |
| transition time | tTHL | 6 | 16 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ | 8 | |
| propagation delay | tPLZ, tPZL | 190 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +125℃ | 8 | ||
| propagation delay | tPLZ, tPZL | 38 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +125℃ | 8 | ||
| propagation delay | tPLZ, tPZL | 32 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +125℃ | 8 | ||
| transition time | tTHL | 110 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +125℃ | 8 | ||
| transition time | tTHL | 22 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +125℃ | 8 | ||
| transition time | tTHL | 19 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +125℃ | 8 | ||
| propagation delay | tPLZ, tPZL | 12 | ns | VCC=5.0V; CL=15pF; Tamb=-40℃ to +85℃ | 8 |
CAD (KiCad official)
- Symbol:
SN74LS01DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls01dr-etched.step/sn74ls01dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls01dr.step/sn74ls01dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (14 pp, sha256
ff190778a023ec5f, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).