SN74HCT74DR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74hct74dr",
  "title": "SN74HCT74DR",
  "brief": "Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "sn74hct74dr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "component": {
    "mpn": "SN74HCT74DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Flip Flops",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74hct74.pdf",
    "parts": {
      "symbol": "sn74hct74dr.kicad_sym",
      "footprint": "sn74hct74dr.kicad_mod",
      "model_3d": "sn74hct74dr-etched.glb",
      "model_3d_plain": "sn74hct74dr.glb",
      "model_3d_step": "sn74hct74dr-etched.step",
      "model_3d_step_plain": "sn74hct74dr.step",
      "lbr": "sn74hct74dr.lbr"
    },
    "distributor_links": {
      "lcsc": "C352961"
    },
    "pins": [
      {
        "number": "1",
        "name": "1CLR",
        "type": "input",
        "description": "Active-low asynchronous clear for flip-flop 1; drives Q1=L, Q̄1=H regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V."
      },
      {
        "number": "2",
        "name": "1D",
        "type": "input",
        "description": "Data input for flip-flop 1; captured on the positive-going CLK edge when PRE and CLR are inactive (high); setup time ≥ 12 ns, hold time ≥ 0 ns at VCC = 4.5 V."
      },
      {
        "number": "3",
        "name": "1CLK",
        "type": "input",
        "description": "Positive-edge clock input for flip-flop 1; TTL-voltage compatible; maximum clock frequency 27 MHz at VCC = 4.5 V."
      },
      {
        "number": "4",
        "name": "1PRE",
        "type": "input",
        "description": "Active-low asynchronous preset for flip-flop 1; drives Q1=H, Q̄1=L regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V."
      },
      {
        "number": "5",
        "name": "1Q",
        "type": "output",
        "description": "Non-inverting output of flip-flop 1; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V); tpd 28 ns typ from CLK at 4.5 V."
      },
      {
        "number": "6",
        "name": "~{1Q}",
        "type": "output",
        "description": "Inverting (complementary) output of flip-flop 1; always the logical complement of 1Q; same drive ratings as 1Q (VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA)."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground supply reference (0 V); continuous current through GND pin ±50 mA maximum."
      },
      {
        "number": "8",
        "name": "~{2Q}",
        "type": "output",
        "description": "Inverting (complementary) output of flip-flop 2; always the logical complement of 2Q; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V)."
      },
      {
        "number": "9",
        "name": "2Q",
        "type": "output",
        "description": "Non-inverting output of flip-flop 2; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V); tpd 28 ns typ from CLK at 4.5 V."
      },
      {
        "number": "10",
        "name": "2PRE",
        "type": "input",
        "description": "Active-low asynchronous preset for flip-flop 2; drives Q2=H, Q̄2=L regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V."
      },
      {
        "number": "11",
        "name": "2CLK",
        "type": "input",
        "description": "Positive-edge clock input for flip-flop 2; TTL-voltage compatible; maximum clock frequency 27 MHz at VCC = 4.5 V."
      },
      {
        "number": "12",
        "name": "2D",
        "type": "input",
        "description": "Data input for flip-flop 2; captured on the positive-going CLK edge when PRE and CLR are inactive (high); setup time ≥ 12 ns, hold time ≥ 0 ns at VCC = 4.5 V."
      },
      {
        "number": "13",
        "name": "2CLR",
        "type": "input",
        "description": "Active-low asynchronous clear for flip-flop 2; drives Q2=L, Q̄2=H regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage; recommended operating range 4.5 V to 5.5 V; quiescent ICC max 40 μA at VCC = 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-4-6",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-7",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 33,
        "cost_usd": 0.4435,
        "at": "2026-09-18T07:21:12"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74hct74.pdf",
        "pages": 33,
        "sha256": "2a239e759861dbe7",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "sn74hct74dr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74hct74dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "ffb2e2b7803759cd66ddc86e358618a71662a8bbd01d852c347eb0b6f6e51b77",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "variants": [],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74hct74dr"
  ],
  "discovery_pitch": "SN74HCT74DR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hct74dr.kicad_sym",
    "sn74hct74dr.kicad_mod",
    "sn74hct74dr.glb",
    "sn74hct74dr.step",
    "sn74hct74dr.lbr",
    "docs/hero.png",
    "docs/sn74hct74dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-25T07:15:29.936Z"
}