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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74HCT74DR

Texas Instruments · Flip Flops · SOIC-14

SN74HCT74DR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1CLR	input	Active-low asynchronous clear for flip-flop 1; drives Q1=L, Q̄1=H regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V.
2	1D	input	Data input for flip-flop 1; captured on the positive-going CLK edge when PRE and CLR are inactive (high); setup time ≥ 12 ns, hold time ≥ 0 ns at VCC = 4.5 V.
3	1CLK	input	Positive-edge clock input for flip-flop 1; TTL-voltage compatible; maximum clock frequency 27 MHz at VCC = 4.5 V.
4	1PRE	input	Active-low asynchronous preset for flip-flop 1; drives Q1=H, Q̄1=L regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V.
5	1Q	output	Non-inverting output of flip-flop 1; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V); tpd 28 ns typ from CLK at 4.5 V.
6	~{1Q}	output	Inverting (complementary) output of flip-flop 1; always the logical complement of 1Q; same drive ratings as 1Q (VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA).
7	GND	power_in	Ground supply reference (0 V); continuous current through GND pin ±50 mA maximum.
8	~{2Q}	output	Inverting (complementary) output of flip-flop 2; always the logical complement of 2Q; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V).
9	2Q	output	Non-inverting output of flip-flop 2; VOH ≥ 3.98 V at IOH = −4 mA, VOL ≤ 0.26 V at IOL = 4 mA (VCC = 4.5 V); tpd 28 ns typ from CLK at 4.5 V.
10	2PRE	input	Active-low asynchronous preset for flip-flop 2; drives Q2=H, Q̄2=L regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V.
11	2CLK	input	Positive-edge clock input for flip-flop 2; TTL-voltage compatible; maximum clock frequency 27 MHz at VCC = 4.5 V.
12	2D	input	Data input for flip-flop 2; captured on the positive-going CLK edge when PRE and CLR are inactive (high); setup time ≥ 12 ns, hold time ≥ 0 ns at VCC = 4.5 V.
13	2CLR	input	Active-low asynchronous clear for flip-flop 2; drives Q2=L, Q̄2=H regardless of other inputs; minimum pulse width 16 ns at VCC = 4.5 V.
14	VCC	power_in	Positive supply voltage; recommended operating range 4.5 V to 5.5 V; quiescent ICC max 40 μA at VCC = 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: SN74HCT74DR
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: sn74hct74dr-etched.step / sn74hct74dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct74dr.step / sn74hct74dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (33 pp, sha256 2a239e759861dbe7, retrieved 2026-09-18, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF