SN74HCS74QPWRQ1

Texas Instruments · Flip Flops · TSSOP-14

SN74HCS74QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1CLR	input	Active low clear input for channel 1; clears the Q output to logic low when asserted.
2	1D	input	Data input for channel 1; sampled on rising clock edge when CLR and PRE are inactive.
3	1CLK	input	Clock input for channel 1, rising edge triggered; latches D input data to Q outputs on rising pulse.
4	1PRE	input	Active low preset input for channel 1; sets the Q output to logic high when asserted.
5	1Q	output	Q output of channel 1 flip-flop; reflects latched state from D input following clock rising edge.
6	1Q̄	output	Inverted Q output for channel 1; always complementary to Q output.
7	GND	power_in	Ground; power supply return terminal.
8	2Q̄	output	Inverted Q output for channel 2; always complementary to Q output.
9	2Q	output	Q output of channel 2 flip-flop; reflects latched state from D input following clock rising edge.
10	2PRE	input	Active low preset input for channel 2; sets the Q output to logic high when asserted.
11	2CLK	input	Clock input for channel 2, rising edge triggered; latches D input data to Q outputs on rising pulse.
12	2D	input	Data input for channel 2; sampled on rising clock edge when CLR and PRE are inactive.
13	2CLR	input	Active low clear input for channel 2; clears the Q output to logic low when asserted.
14	VCC	power_in	Positive supply voltage; operating range 2V to 6V with output drive capability of ±7.8mA at 6V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Logic
Pins	14

CAD (KiCad official)

Symbol: SN74HCS74QPWRQ1
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: sn74hcs74qpwrq1-etched.step / sn74hcs74qpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs74qpwrq1.step / sn74hcs74qpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 f2e488eb90d39065, retrieved 2026-10-03, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# SN74HCS74QPWRQ1

**Texas Instruments** · Flip Flops · TSSOP-14

SN74HCS74QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CLR | input | Active low clear input for channel 1; clears the Q output to logic low when asserted. |
| 2 | 1D | input | Data input for channel 1; sampled on rising clock edge when CLR and PRE are inactive. |
| 3 | 1CLK | input | Clock input for channel 1, rising edge triggered; latches D input data to Q outputs on rising pulse. |
| 4 | 1PRE | input | Active low preset input for channel 1; sets the Q output to logic high when asserted. |
| 5 | 1Q | output | Q output of channel 1 flip-flop; reflects latched state from D input following clock rising edge. |
| 6 | 1Q̄ | output | Inverted Q output for channel 1; always complementary to Q output. |
| 7 | GND | power_in | Ground; power supply return terminal. |
| 8 | 2Q̄ | output | Inverted Q output for channel 2; always complementary to Q output. |
| 9 | 2Q | output | Q output of channel 2 flip-flop; reflects latched state from D input following clock rising edge. |
| 10 | 2PRE | input | Active low preset input for channel 2; sets the Q output to logic high when asserted. |
| 11 | 2CLK | input | Clock input for channel 2, rising edge triggered; latches D input data to Q outputs on rising pulse. |
| 12 | 2D | input | Data input for channel 2; sampled on rising clock edge when CLR and PRE are inactive. |
| 13 | 2CLR | input | Active low clear input for channel 2; clears the Q output to logic low when asserted. |
| 14 | VCC | power_in | Positive supply voltage; operating range 2V to 6V with output drive capability of ±7.8mA at 6V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `SN74HCS74QPWRQ1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74hcs74qpwrq1-etched.step` / `sn74hcs74qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs74qpwrq1.step` / `sn74hcs74qpwrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hcs74-q1) (34 pp, sha256 `f2e488eb90d39065`, retrieved 2026-10-03, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hcs74qpwrq1-datasheet.pdf)