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SN74HCS74QPWRQ1
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Texas Instruments Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# SN74HCS74QPWRQ1++**Texas Instruments** · Flip Flops · TSSOP-14++SN74HCS74QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Active low clear input for channel 1; clears the Q output to logic low when asserted. |+| 2 | 1D | input | Data input for channel 1; sampled on rising clock edge when CLR and PRE are inactive. |+| 3 | 1CLK | input | Clock input for channel 1, rising edge triggered; latches D input data to Q outputs on rising pulse. |+| 4 | 1PRE | input | Active low preset input for channel 1; sets the Q output to logic high when asserted. |+| 5 | 1Q | output | Q output of channel 1 flip-flop; reflects latched state from D input following clock rising edge. |+| 6 | 1Q̄ | output | Inverted Q output for channel 1; always complementary to Q output. |+| 7 | GND | power_in | Ground; power supply return terminal. |+| 8 | 2Q̄ | output | Inverted Q output for channel 2; always complementary to Q output. |+| 9 | 2Q | output | Q output of channel 2 flip-flop; reflects latched state from D input following clock rising edge. |+| 10 | 2PRE | input | Active low preset input for channel 2; sets the Q output to logic high when asserted. |+| 11 | 2CLK | input | Clock input for channel 2, rising edge triggered; latches D input data to Q outputs on rising pulse. |+| 12 | 2D | input | Data input for channel 2; sampled on rising clock edge when CLR and PRE are inactive. |+| 13 | 2CLR | input | Active low clear input for channel 2; clears the Q output to logic low when asserted. |+| 14 | VCC | power_in | Positive supply voltage; operating range 2V to 6V with output drive capability of ±7.8mA at 6V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74HCS74QPWRQ1`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74hcs74qpwrq1-etched.step` / `sn74hcs74qpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hcs74qpwrq1.step` / `sn74hcs74qpwrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hcs74-q1) (34 pp, sha256 `f2e488eb90d39065`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hcs74qpwrq1-datasheet.pdf)
page.jsonadded+194@@ -0,0 +1,194 @@+{+ "slug": "sn74hcs74qpwrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74hcs74qpwrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74hcs74qpwrq1.kicad_sym",+ "sn74hcs74qpwrq1.kicad_mod",+ "sn74hcs74qpwrq1.glb",+ "sn74hcs74qpwrq1.step",+ "sn74hcs74qpwrq1.lbr",+ "docs/hero.png",+ "docs/sn74hcs74qpwrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74hcs74qpwrq1-hero.glb",+ "sn74hcs74qpwrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74HCS74QPWRQ1",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74hcs74-q1",+ "parts": {+ "symbol": "sn74hcs74qpwrq1.kicad_sym",+ "footprint": "sn74hcs74qpwrq1.kicad_mod",+ "model_3d": "sn74hcs74qpwrq1-hero.glb",+ "model_3d_plain": "sn74hcs74qpwrq1.glb",+ "model_3d_step": "sn74hcs74qpwrq1-etched.step",+ "model_3d_step_plain": "sn74hcs74qpwrq1.step",+ "lbr": "sn74hcs74qpwrq1.lbr"+ },+ "distributor_links": {+ "lcsc": 2846790,+ "digikey": "296-53596-2-ND",+ "mouser": "595-SN74HCS74QPWRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T09:23:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-53596-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74HCS74QPWRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1CLR",+ "type": "input",+ "description": "Active low clear input for channel 1; clears the Q output to logic low when asserted."+ },+ {+ "number": "2",+ "name": "1D",+ "type": "input",+ "description": "Data input for channel 1; sampled on rising clock edge when CLR and PRE are inactive."+ },+ {+ "number": "3",+ "name": "1CLK",+ "type": "input",+ "description": "Clock input for channel 1, rising edge triggered; latches D input data to Q outputs on rising pulse."+ },+ {+ "number": "4",+ "name": "1PRE",+ "type": "input",+ "description": "Active low preset input for channel 1; sets the Q output to logic high when asserted."+ },+ {+ "number": "5",+ "name": "1Q",+ "type": "output",+ "description": "Q output of channel 1 flip-flop; reflects latched state from D input following clock rising edge."+ },+ {+ "number": "6",+ "name": "1Q̄",+ "type": "output",+ "description": "Inverted Q output for channel 1; always complementary to Q output."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; power supply return terminal."+ },+ {+ "number": "8",+ "name": "2Q̄",+ "type": "output",+ "description": "Inverted Q output for channel 2; always complementary to Q output."+ },+ {+ "number": "9",+ "name": "2Q",+ "type": "output",+ "description": "Q output of channel 2 flip-flop; reflects latched state from D input following clock rising edge."+ },+ {+ "number": "10",+ "name": "2PRE",+ "type": "input",+ "description": "Active low preset input for channel 2; sets the Q output to logic high when asserted."+ },+ {+ "number": "11",+ "name": "2CLK",+ "type": "input",+ "description": "Clock input for channel 2, rising edge triggered; latches D input data to Q outputs on rising pulse."+ },+ {+ "number": "12",+ "name": "2D",+ "type": "input",+ "description": "Data input for channel 2; sampled on rising clock edge when CLR and PRE are inactive."+ },+ {+ "number": "13",+ "name": "2CLR",+ "type": "input",+ "description": "Active low clear input for channel 2; clears the Q output to logic low when asserted."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; operating range 2V to 6V with output drive capability of ±7.8mA at 6V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 7,+ "cost_usd": 0.1076,+ "at": "2026-10-03T09:23:23"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74hcs74-q1",+ "pages": 34,+ "sha256": "f2e488eb90d39065",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}