SN74HC597DR

{
  "slug": "sn74hc597dr",
  "version": "0.1.0",
  "type": "component",
  "description": "lingxingic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "sn74hc597dr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74hc597dr.kicad_sym",
    "sn74hc597dr.kicad_mod",
    "sn74hc597dr.glb",
    "sn74hc597dr.step",
    "sn74hc597dr.lbr",
    "docs/hero.png",
    "docs/sn74hc597dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "sn74hc597dr-hero.glb",
    "sn74hc597dr-hero.overlay.json",
    "sn74hc597dr-etched.glb"
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  "component": {
    "mpn": "SN74HC597DR",
    "manufacturer": "lingxingic",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shift Registers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603352564889243648",
    "parts": {
      "symbol": "sn74hc597dr.kicad_sym",
      "footprint": "sn74hc597dr.kicad_mod",
      "model_3d": "sn74hc597dr-hero.glb",
      "model_3d_plain": "sn74hc597dr-etched.glb",
      "model_3d_step": "sn74hc597dr-etched.step",
      "model_3d_step_plain": "sn74hc597dr.step",
      "lbr": "sn74hc597dr.lbr"
    },
    "distributor_links": {
      "lcsc": "C24833619"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T13:32:47Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "D1",
        "type": "output",
        "description": "Parallel data output D1 of the 8-bit register, per the pin description table."
      },
      {
        "number": "2",
        "name": "D2",
        "type": "output",
        "description": "Parallel data output D2 of the 8-bit register, per the pin description table."
      },
      {
        "number": "3",
        "name": "D3",
        "type": "output",
        "description": "Parallel data output D3 of the 8-bit register, per the pin description table."
      },
      {
        "number": "4",
        "name": "D4",
        "type": "output",
        "description": "Parallel data output D4 of the 8-bit register, per the pin description table."
      },
      {
        "number": "5",
        "name": "D5",
        "type": "output",
        "description": "Parallel data output D5 of the 8-bit register, per the pin description table."
      },
      {
        "number": "6",
        "name": "D6",
        "type": "output",
        "description": "Parallel data output D6 of the 8-bit register, per the pin description table."
      },
      {
        "number": "7",
        "name": "D7",
        "type": "output",
        "description": "Parallel data output D7 of the 8-bit register, per the pin description table."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V) for the device; voltages are referenced to GND."
      },
      {
        "number": "9",
        "name": "Q",
        "type": "output",
        "description": "Serial data output of the shift register."
      },
      {
        "number": "10",
        "name": "MR",
        "type": "input",
        "description": "Asynchronous master reset input, active LOW; a LOW level clears the shift register."
      },
      {
        "number": "11",
        "name": "SHCP",
        "type": "input",
        "description": "Shift register clock input, edge-triggered on the LOW-to-HIGH transition."
      },
      {
        "number": "12",
        "name": "STCP",
        "type": "input",
        "description": "Storage register clock input, edge-triggered on the LOW-to-HIGH transition."
      },
      {
        "number": "13",
        "name": "PL",
        "type": "input",
        "description": "Parallel load input, active LOW; when LOW, data is loaded from the inputs to the shift register per the function table."
      },
      {
        "number": "14",
        "name": "DS",
        "type": "input",
        "description": "Serial data input to the first stage of the shift register (Q0 = DS on SHCP rising edge)."
      },
      {
        "number": "15",
        "name": "D0",
        "type": "input",
        "description": "Parallel data input D0, loaded through the input flip-flops on the STCP clock."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; the datasheet's recommended range is 2.0 V to 6.0 V for the HC type and 4.5 V to 5.5 V for the HCT type."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin configuration diagram on page 6 is an image and not present in the extracted text. Pin numbe; Package confirmed as SOP16: the ordering table on page 5 lists SN74HC597DR(LX) in SOP16 reel packing; The datasheet covers both SN74HC597 and SN74HCT597 variants. Pin assignments are the same for both, "
        ],
        "pages_sent": 23,
        "cost_usd": 0.0871,
        "at": "2026-10-18T13:30:10"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603352564889243648",
        "pages": 23,
        "sha256": "7361c76bd337f88f",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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      "footprint": "viewers/footprint.html"
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
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        "checked": "2026-10-18",
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      },
      {
        "file": "sn74hc597dr-etched.step",
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        "sha256": "b93ab49ef4ee9d10d1ae8f9250bfd654e4b460e24398589797dfe0ccdb2866e2",
        "checked": "2026-10-18",
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      }
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  }
}