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SN74HC597DR
Public Made by Adomby adom
lingxingic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC597DR
lingxingic · Shift Registers · SOP-16
SN74HC597DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | output | Parallel data output D1 of the 8-bit register, per the pin description table. |
| 2 | D2 | output | Parallel data output D2 of the 8-bit register, per the pin description table. |
| 3 | D3 | output | Parallel data output D3 of the 8-bit register, per the pin description table. |
| 4 | D4 | output | Parallel data output D4 of the 8-bit register, per the pin description table. |
| 5 | D5 | output | Parallel data output D5 of the 8-bit register, per the pin description table. |
| 6 | D6 | output | Parallel data output D6 of the 8-bit register, per the pin description table. |
| 7 | D7 | output | Parallel data output D7 of the 8-bit register, per the pin description table. |
| 8 | GND | power_in | Ground reference (0 V) for the device; voltages are referenced to GND. |
| 9 | Q | output | Serial data output of the shift register. |
| 10 | MR | input | Asynchronous master reset input, active LOW; a LOW level clears the shift register. |
| 11 | SHCP | input | Shift register clock input, edge-triggered on the LOW-to-HIGH transition. |
| 12 | STCP | input | Storage register clock input, edge-triggered on the LOW-to-HIGH transition. |
| 13 | PL | input | Parallel load input, active LOW; when LOW, data is loaded from the inputs to the shift register per the function table. |
| 14 | DS | input | Serial data input to the first stage of the shift register (Q0 = DS on SHCP rising edge). |
| 15 | D0 | input | Parallel data input D0, loaded through the input flip-flops on the STCP clock. |
| 16 | VCC | power_in | Supply voltage; the datasheet's recommended range is 2.0 V to 6.0 V for the HC type and 4.5 V to 5.5 V for the HCT type. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 8 | ||
| supply current | ICC | 50 | mA | 8 | |||
| ground current | IGND | -50 | mA | 8 | |||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 8 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 8 | |
| output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 8 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| soldering temperature | TL | 260 | ℃ | 10s SOP/TSSOP | 8 | ||
| supply voltage (HC) | VCC | 2 | 5 | 6 | V | 8 | |
| input voltage | VI | 0 | V | 8 | |||
| output voltage | VO | 0 | V | 8 | |||
| ambient temperature | Tamb | -40 | 125 | ℃ | 8 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC 2.0V (Tamb -40 to +85 C) | 9 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC 4.5V (Tamb -40 to +85 C) | 9 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC 6.0V (Tamb -40 to +85 C) | 9 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC 2.0V (Tamb -40 to +85 C) | 9 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC 4.5V (Tamb -40 to +85 C) | 9 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC 6.0V (Tamb -40 to +85 C) | 9 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VCC 2.0V; IO=-20uA (Tamb -40 to +85 C) | 9 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VCC 4.5V; IO=-20uA (Tamb -40 to +85 C) | 9 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VCC 6.0V; IO=-20uA (Tamb -40 to +85 C) | 9 | |
| HIGH-level output voltage | VOH | 3.84 | 4.32 | V | VCC 4.5V; IO=-4.0mA (Tamb -40 to +85 C) | 9 | |
| HIGH-level output voltage | VOH | 5.34 | 5.81 | V | VCC 6.0V; IO=-5.2mA (Tamb -40 to +85 C) | 9 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VCC 2.0V; IO=20uA (Tamb -40 to +85 C) | 9 | |
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | VCC 4.5V; IO=4.0mA (Tamb -40 to +85 C) | 9 | |
| LOW-level output voltage | VOL | 0.16 | 0.33 | V | VCC 6.0V; IO=5.2mA (Tamb -40 to +85 C) | 9 | |
| input leakage current | II | -2 | 2 | uA | VCC 6.0V; VI=VCC or GND (Tamb -40 to +85 C) | 9 | |
| supply current | ICC | 80 | uA | VCC 6.0V; VI=VCC or GND; IO=0A (Tamb -40 to +85 C) | 9 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC 2.0V (Tamb -40 to +125 C) | 10 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC 4.5V (Tamb -40 to +125 C) | 10 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC 6.0V (Tamb -40 to +125 C) | 10 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC 2.0V (Tamb -40 to +125 C) | 10 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC 4.5V (Tamb -40 to +125 C) | 10 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC 6.0V (Tamb -40 to +125 C) | 10 | ||
| HIGH-level output voltage | VOH | 1.9 | V | VCC 2.0V; IO=-20uA (Tamb -40 to +125 C) | 10 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VCC 4.5V; IO=-20uA (Tamb -40 to +125 C) | 10 | ||
| HIGH-level output voltage | VOH | 5.9 | V | VCC 6.0V; IO=-20uA (Tamb -40 to +125 C) | 10 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VCC 4.5V; IO=-4.0mA (Tamb -40 to +125 C) | 10 | ||
| HIGH-level output voltage | VOH | 5.2 | V | VCC 6.0V; IO=-5.2mA (Tamb -40 to +125 C) | 10 | ||
| LOW-level output voltage | VOL | 0.1 | V | VCC 2.0V; IO=20uA (Tamb -40 to +125 C) | 10 | ||
| LOW-level output voltage | VOL | 0.4 | V | VCC 4.5V; IO=4.0mA (Tamb -40 to +125 C) | 10 | ||
| input leakage current | II | -4 | 4 | uA | VCC 6.0V; VI=VCC or GND (Tamb -40 to +125 C) | 10 | |
| supply current | ICC | 160 | uA | VCC 6.0V; VI=VCC or GND; IO=0A (Tamb -40 to +125 C) | 10 | ||
| SHCP to Q propagation delay | tPLH, tPHL | 20 | 44 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +85 C) | 11 | |
| MR to Q propagation delay | tPLH, tPHL | 21 | 44 | ns | VCC 4.5V; CL=50pF; see Figure 6 (Tamb -40 to +85 C) | 11 | |
| STCP to Q propagation delay | tPLH, tPHL | 29 | 63 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +85 C) | 11 | |
| PL to Q propagation delay | tPLH, tPHL | 25 | 54 | ns | VCC 4.5V; CL=50pF; see Figure 7 (Tamb -40 to +85 C) | 11 | |
| transition time | tt | 7 | 19 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +85 C) | 11 | |
| SHCP maximum frequency | fmax | 24 | 87 | MHZ | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +85 C) | 11 | |
| STCP pulse width (HIGH or LOW) | tw | 20 | 4 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +85 C) | 11 | |
| Dn to STCP set-up time | tsu | 15 | 3 | ns | VCC 4.5V; CL=50pF; see Figure 9 (Tamb -40 to +85 C) | 11 | |
| SHCP to Q propagation delay | tPLH, tPHL | 53 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +125 C) | 14 | ||
| STCP to Q propagation delay | tPLH, tPHL | 75 | ns | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +125 C) | 14 | ||
| SHCP maximum frequency | fmax | 24 | MHZ | VCC 4.5V; CL=50pF; see Figure 5 (Tamb -40 to +125 C) | 14 |
CAD (KiCad official)
- Symbol:
SN74HC597DR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc597dr-etched.step/sn74hc597dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc597dr.step/sn74hc597dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (23 pp, sha256
7361c76bd337f88f, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).