SN74HC590ADWR

Texas Instruments · Counters, Dividers · SOIC-16

SN74HC590ADWR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	QB	tri_state	Parallel 3-state register output QB of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
2	QC	tri_state	Parallel 3-state register output QC of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
3	QD	tri_state	Parallel 3-state register output QD of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
4	QE	tri_state	Parallel 3-state register output QE of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
5	QF	tri_state	Parallel 3-state register output QF of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
6	QG	tri_state	Parallel 3-state register output QG of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
7	QH	tri_state	Parallel 3-state register output QH of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
8	GND	power_in	Ground reference for the device.
9	RCO	output	Ripple-carry output for cascading; it is connected to CCKEN of a second stage for two-stage expansion or to CCLK of the following stage for longer chains, and is driven by CCLK rising edges (tpd CCLK↑ to RCO).
10	CCLR	input	Direct (asynchronous) clear input for the binary counter; a low level clears the counter independently of CCLK, and the datasheet specifies a minimum CCLR low pulse width.
11	CCLK	input	Counter clock input, positive-edge triggered; if tied to RCLK the register is one count behind the counter.
12	CCKEN	input	Counter clock enable; a high level inhibits the counter clock (CCKEN must be low before CCLK rises, with listed setup and hold times).
13	RCLK	input	Storage register clock input, positive-edge triggered, which transfers the counter state to the 8-bit output register; it must be set up before the register clock edge relative to CCLK, with the listed timing limits.
14	OE	input	Output enable for QA-QH; the switching characteristics show outputs enabled on OE going low and placed in 3-state on OE going high.
15	QA	tri_state	Parallel 3-state register output QA of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads.
16	VCC	power_in	Supply voltage, specified from 2 V to 6 V with absolute maximum of 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: SN74HC590ADWR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: sn74hc590adwr-etched.step / sn74hc590adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc590adwr.step / sn74hc590adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (26 pp, sha256 15f4b455093631e3, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# SN74HC590ADWR

**Texas Instruments** · Counters, Dividers · SOIC-16

SN74HC590ADWR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | tri_state | Parallel 3-state register output QB of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 2 | QC | tri_state | Parallel 3-state register output QC of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 3 | QD | tri_state | Parallel 3-state register output QD of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 4 | QE | tri_state | Parallel 3-state register output QE of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 5 | QF | tri_state | Parallel 3-state register output QF of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 6 | QG | tri_state | Parallel 3-state register output QG of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 7 | QH | tri_state | Parallel 3-state register output QH of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | RCO | output | Ripple-carry output for cascading; it is connected to CCKEN of a second stage for two-stage expansion or to CCLK of the following stage for longer chains, and is driven by CCLK rising edges (tpd CCLK↑ to RCO). |
| 10 | CCLR | input | Direct (asynchronous) clear input for the binary counter; a low level clears the counter independently of CCLK, and the datasheet specifies a minimum CCLR low pulse width. |
| 11 | CCLK | input | Counter clock input, positive-edge triggered; if tied to RCLK the register is one count behind the counter. |
| 12 | CCKEN | input | Counter clock enable; a high level inhibits the counter clock (CCKEN must be low before CCLK rises, with listed setup and hold times). |
| 13 | RCLK | input | Storage register clock input, positive-edge triggered, which transfers the counter state to the 8-bit output register; it must be set up before the register clock edge relative to CCLK, with the listed timing limits. |
| 14 | OE | input | Output enable for QA-QH; the switching characteristics show outputs enabled on OE going low and placed in 3-state on OE going high. |
| 15 | QA | tri_state | Parallel 3-state register output QA of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |
| 16 | VCC | power_in | Supply voltage, specified from 2 V to 6 V with absolute maximum of 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74HC590ADWR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74hc590adwr-etched.step` / `sn74hc590adwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc590adwr.step` / `sn74hc590adwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc590a) (26 pp, sha256 `15f4b455093631e3`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74hc590adwr-datasheet.pdf)