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SN74HC590ADWR
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Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN74HC590ADWR++**Texas Instruments** · Counters, Dividers · SOIC-16++SN74HC590ADWR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Parallel 3-state register output QB of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 2 | QC | tri_state | Parallel 3-state register output QC of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 3 | QD | tri_state | Parallel 3-state register output QD of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 4 | QE | tri_state | Parallel 3-state register output QE of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 5 | QF | tri_state | Parallel 3-state register output QF of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 6 | QG | tri_state | Parallel 3-state register output QG of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 7 | QH | tri_state | Parallel 3-state register output QH of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 8 | GND | power_in | Ground reference for the device. |+| 9 | RCO | output | Ripple-carry output for cascading; it is connected to CCKEN of a second stage for two-stage expansion or to CCLK of the following stage for longer chains, and is driven by CCLK rising edges (tpd CCLK↑ to RCO). |+| 10 | CCLR | input | Direct (asynchronous) clear input for the binary counter; a low level clears the counter independently of CCLK, and the datasheet specifies a minimum CCLR low pulse width. |+| 11 | CCLK | input | Counter clock input, positive-edge triggered; if tied to RCLK the register is one count behind the counter. |+| 12 | CCKEN | input | Counter clock enable; a high level inhibits the counter clock (CCKEN must be low before CCLK rises, with listed setup and hold times). |+| 13 | RCLK | input | Storage register clock input, positive-edge triggered, which transfers the counter state to the 8-bit output register; it must be set up before the register clock edge relative to CCLK, with the listed timing limits. |+| 14 | OE | input | Output enable for QA-QH; the switching characteristics show outputs enabled on OE going low and placed in 3-state on OE going high. |+| 15 | QA | tri_state | Parallel 3-state register output QA of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads. |+| 16 | VCC | power_in | Supply voltage, specified from 2 V to 6 V with absolute maximum of 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74HC590ADWR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn74hc590adwr-etched.step` / `sn74hc590adwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc590adwr.step` / `sn74hc590adwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74hc590a) (26 pp, sha256 `15f4b455093631e3`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74hc590adwr-datasheet.pdf)
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it is connected to CCKEN of a second stage for two-stage expansion or to CCLK of the following stage for longer chains, and is driven by CCLK rising edges (tpd CCLK↑ to RCO)."+ },+ {+ "number": "10",+ "name": "CCLR",+ "type": "input",+ "description": "Direct (asynchronous) clear input for the binary counter; a low level clears the counter independently of CCLK, and the datasheet specifies a minimum CCLR low pulse width."+ },+ {+ "number": "11",+ "name": "CCLK",+ "type": "input",+ "description": "Counter clock input, positive-edge triggered; if tied to RCLK the register is one count behind the counter."+ },+ {+ "number": "12",+ "name": "CCKEN",+ "type": "input",+ "description": "Counter clock enable; a high level inhibits the counter clock (CCKEN must be low before CCLK rises, with listed setup and hold times)."+ },+ {+ "number": "13",+ "name": "RCLK",+ "type": "input",+ "description": "Storage register clock input, positive-edge triggered, which transfers the counter state to the 8-bit output register; it must be set up before the register clock edge relative to CCLK, with the listed timing limits."+ },+ {+ "number": "14",+ "name": "OE",+ "type": "input",+ "description": "Output enable for QA-QH; the switching characteristics show outputs enabled on OE going low and placed in 3-state on OE going high."+ },+ {+ "number": "15",+ "name": "QA",+ "type": "tri_state",+ "description": "Parallel 3-state register output QA of the 8-bit storage register, which is loaded from the counter on the RCLK rising edge and drives up to 15 LSTTL loads."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, specified from 2 V to 6 V with absolute maximum of 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the top-view pin diagram on page 1 and cross-checked against the logic diagram on ; The datasheet does not explicitly state the polarity of OE; the active-low enable and high-level 3-s; Pin descriptions for RCLK, CCLK, CCKEN and CCLR are summarised from the timing and function text; no"+ ],+ "pages_sent": 26,+ "cost_usd": 0.0933,+ "at": "2026-10-08T20:05:35"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74hc590a",+ "pages": 26,+ "sha256": "15f4b455093631e3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74hc590adwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74hc590adwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3d42a6c792e1a0f962c00ebf4dacfb5935a32274a3011dc38d062bb41220f9dd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}