component
SN74HC374D
Public Made by Adomby adom
lingxingic Flip Flops, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74HC374D
lingxingic · Flip Flops · SOP-20-300mil
SN74HC374D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable; when OE is high the Q0-Q7 outputs are forced to high impedance, and OE changes do not affect the flip-flop state. |
| 2 | Q0 | tri_state | Three-state non-inverted data output of flip-flop 0, high impedance when OE is high. |
| 3 | D0 | input | Data input to flip-flop 0, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 4 | D1 | input | Data input to flip-flop 1, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 5 | Q1 | tri_state | Three-state non-inverted data output of flip-flop 1, high impedance when OE is high. |
| 6 | Q2 | tri_state | Three-state non-inverted data output of flip-flop 2, high impedance when OE is high. |
| 7 | D2 | input | Data input to flip-flop 2, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 8 | D3 | input | Data input to flip-flop 3, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 9 | Q3 | tri_state | Three-state non-inverted data output of flip-flop 3, high impedance when OE is high. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; data is latched on the low-to-high (rising) edge, with setup and hold times per the AC characteristics. |
| 12 | Q4 | tri_state | Three-state non-inverted data output of flip-flop 4, high impedance when OE is high. |
| 13 | D4 | input | Data input to flip-flop 4, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 14 | D5 | input | Data input to flip-flop 5, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 15 | Q5 | tri_state | Three-state non-inverted data output of flip-flop 5, high impedance when OE is high. |
| 16 | Q6 | tri_state | Three-state non-inverted data output of flip-flop 6, high impedance when OE is high. |
| 17 | D6 | input | Data input to flip-flop 6, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 18 | D7 | input | Data input to flip-flop 7, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 19 | Q7 | tri_state | Three-state non-inverted data output of flip-flop 7, high impedance when OE is high. |
| 20 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V for SN74HC374 and 4.5 V to 5.5 V for SN74HCT374. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 6 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 6 | |
| Output current | IO | -35 | 35 | mA | -0.5V<VO<VCC+0.5V | 6 | |
| Supply current | ICC | 70 | mA | 6 | |||
| Ground current | IGND | -70 | mA | 6 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 6 | ||
| Total power dissipation | Ptot | 500 | mW | 6 | |||
| Soldering temperature | TL | 260 | ℃ | 10秒; SOP/TSSOP/SOP(M) | 6 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | SN74HC374 | 7 |
| Input voltage | VI | 0 | V | SN74HC374; max printed as VCC | 7 | ||
| Output voltage | VO | 0 | V | SN74HC374; max printed as VCC | 7 | ||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | SN74HC374 | 7 | |
| High-level input voltage | VIH | 1.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 9 | ||
| High-level input voltage | VIH | 3.15 | V | Tamb=-40℃～+125℃; VCC=4.5V | 9 | ||
| High-level input voltage | VIH | 4.2 | V | Tamb=-40℃～+125℃; VCC=6.0V | 9 | ||
| Low-level input voltage | VIL | 0.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 9 | ||
| Low-level input voltage | VIL | 1.35 | V | Tamb=-40℃～+125℃; VCC=4.5V | 9 | ||
| Low-level input voltage | VIL | 1.8 | V | Tamb=-40℃～+125℃; VCC=6.0V | 9 | ||
| High-level output voltage | VOH | 1.9 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 9 | ||
| High-level output voltage | VOH | 4.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 9 | ||
| High-level output voltage | VOH | 5.9 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 9 | ||
| High-level output voltage | VOH | 3.7 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-6.0mA; VCC=4.5V | 9 | ||
| High-level output voltage | VOH | 5.2 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-7.8mA; VCC=6.0V | 9 | ||
| Low-level output voltage | VOL | 0.1 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 9 | ||
| Low-level output voltage | VOL | 0.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=6.0mA; VCC=4.5V | 9 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; VCC=6.0V | 9 | |
| Off-state output current | IOZ | -10 | 10 | uA | Tamb=-40℃～+125℃; VI=VIH或VIL; VCC=6.0V; VO=VCC或GND | 9 | |
| Quiescent supply current | ICC | 160 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 9 | ||
| CP to Qn propagation delay | tpd | 250 | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 | ||
| CP to Qn propagation delay | tpd | 50 | ns | Tamb=-40℃～+125℃; 见图6; VCC=4.5V | 13 | ||
| CP to Qn propagation delay | tpd | 43 | ns | Tamb=-40℃～+125℃; 见图6; VCC=6.0V | 13 | ||
| OE to Qn enable time | ten | 225 | ns | Tamb=-40℃～+125℃; 见图7; VCC=2.0V | 13 | ||
| OE to Qn enable time | ten | 45 | ns | Tamb=-40℃～+125℃; 见图7; VCC=4.5V | 13 | ||
| OE to Qn enable time | ten | 38 | ns | Tamb=-40℃～+125℃; 见图7; VCC=6.0V | 13 | ||
| OE to Qn disable time | tdis | 225 | ns | Tamb=-40℃～+125℃; 见图7; VCC=2.0V | 13 | ||
| OE to Qn disable time | tdis | 45 | ns | Tamb=-40℃～+125℃; 见图7; VCC=4.5V | 13 | ||
| OE to Qn disable time | tdis | 38 | ns | Tamb=-40℃～+125℃; 见图7; VCC=6.0V | 13 | ||
| Qn output transition time | tt | 90 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=2.0V | 13 | ||
| Qn output transition time | tt | 18 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=4.5V | 13 | ||
| Qn output transition time | tt | 15 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=6.0V | 13 | ||
| CP pulse width | tW | 120 | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=2.0V | 13 | ||
| CP pulse width | tW | 24 | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=4.5V | 13 | ||
| CP pulse width | tW | 20 | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=6.0V | 13 | ||
| Dn to CP setup time | tsu | 90 | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 | ||
| Dn to CP setup time | tsu | 18 | ns | Tamb=-40℃～+125℃; 见图6; VCC=4.5V | 13 | ||
| Dn to CP setup time | tsu | 15 | ns | Tamb=-40℃～+125℃; 见图6; VCC=6.0V | 13 | ||
| Dn to CP hold time | th | 5 | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 | ||
| Maximum clock frequency | fmax | 4 | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=2.0V | 13 | ||
| Maximum clock frequency | fmax | 20 | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=4.5V | 13 | ||
| Maximum clock frequency | fmax | 24 | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=6.0V | 13 |
CAD (KiCad official)
- Symbol:
SN74HC374D - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sn74hc374d-etched.step/sn74hc374d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc374d.step/sn74hc374d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (21 pp, sha256
e6d21ba7a671b3e3, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74HC374D
**lingxingic** · Flip Flops · SOP-20-300mil
SN74HC374D from lingxingic, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable; when OE is high the Q0-Q7 outputs are forced to high impedance, and OE changes do not affect the flip-flop state. |
| 2 | Q0 | tri_state | Three-state non-inverted data output of flip-flop 0, high impedance when OE is high. |
| 3 | D0 | input | Data input to flip-flop 0, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 4 | D1 | input | Data input to flip-flop 1, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 5 | Q1 | tri_state | Three-state non-inverted data output of flip-flop 1, high impedance when OE is high. |
| 6 | Q2 | tri_state | Three-state non-inverted data output of flip-flop 2, high impedance when OE is high. |
| 7 | D2 | input | Data input to flip-flop 2, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 8 | D3 | input | Data input to flip-flop 3, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 9 | Q3 | tri_state | Three-state non-inverted data output of flip-flop 3, high impedance when OE is high. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; data is latched on the low-to-high (rising) edge, with setup and hold times per the AC characteristics. |
| 12 | Q4 | tri_state | Three-state non-inverted data output of flip-flop 4, high impedance when OE is high. |
| 13 | D4 | input | Data input to flip-flop 4, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 14 | D5 | input | Data input to flip-flop 5, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 15 | Q5 | tri_state | Three-state non-inverted data output of flip-flop 5, high impedance when OE is high. |
| 16 | Q6 | tri_state | Three-state non-inverted data output of flip-flop 6, high impedance when OE is high. |
| 17 | D6 | input | Data input to flip-flop 6, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 18 | D7 | input | Data input to flip-flop 7, stored on the rising edge of CP; input has internal clamp diodes allowing voltages above VCC through a series resistor. |
| 19 | Q7 | tri_state | Three-state non-inverted data output of flip-flop 7, high impedance when OE is high. |
| 20 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V for SN74HC374 and 4.5 V to 5.5 V for SN74HCT374. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 6 |
| Input clamp current | IIK | -20 | | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 6 |
| Output clamp current | IOK | -20 | | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 6 |
| Output current | IO | -35 | | 35 | mA | -0.5V<VO<VCC+0.5V | 6 |
| Supply current | ICC | | | 70 | mA | | 6 |
| Ground current | IGND | -70 | | | mA | | 6 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 6 |
| Total power dissipation | Ptot | | | 500 | mW | | 6 |
| Soldering temperature | TL | | | 260 | ℃ | 10秒; SOP/TSSOP/SOP(M) | 6 |
| Supply voltage | VCC | 2 | 5 | 6 | V | SN74HC374 | 7 |
| Input voltage | VI | 0 | | | V | SN74HC374; max printed as VCC | 7 |
| Output voltage | VO | 0 | | | V | SN74HC374; max printed as VCC | 7 |
| Input rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 7 |
| Input rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 7 |
| Input rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 7 |
| Operating ambient temperature | Tamb | -40 | | 125 | ℃ | SN74HC374 | 7 |
| High-level input voltage | VIH | 1.5 | | | V | Tamb=-40℃～+125℃; VCC=2.0V | 9 |
| High-level input voltage | VIH | 3.15 | | | V | Tamb=-40℃～+125℃; VCC=4.5V | 9 |
| High-level input voltage | VIH | 4.2 | | | V | Tamb=-40℃～+125℃; VCC=6.0V | 9 |
| Low-level input voltage | VIL | | | 0.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 9 |
| Low-level input voltage | VIL | | | 1.35 | V | Tamb=-40℃～+125℃; VCC=4.5V | 9 |
| Low-level input voltage | VIL | | | 1.8 | V | Tamb=-40℃～+125℃; VCC=6.0V | 9 |
| High-level output voltage | VOH | 1.9 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V | 9 |
| High-level output voltage | VOH | 4.4 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V | 9 |
| High-level output voltage | VOH | 5.9 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V | 9 |
| High-level output voltage | VOH | 3.7 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-6.0mA; VCC=4.5V | 9 |
| High-level output voltage | VOH | 5.2 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-7.8mA; VCC=6.0V | 9 |
| Low-level output voltage | VOL | | | 0.1 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=20uA; VCC=2.0V | 9 |
| Low-level output voltage | VOL | | | 0.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=6.0mA; VCC=4.5V | 9 |
| Input leakage current | II | -1 | | 1 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; VCC=6.0V | 9 |
| Off-state output current | IOZ | -10 | | 10 | uA | Tamb=-40℃～+125℃; VI=VIH或VIL; VCC=6.0V; VO=VCC或GND | 9 |
| Quiescent supply current | ICC | | | 160 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 9 |
| CP to Qn propagation delay | tpd | | | 250 | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 |
| CP to Qn propagation delay | tpd | | | 50 | ns | Tamb=-40℃～+125℃; 见图6; VCC=4.5V | 13 |
| CP to Qn propagation delay | tpd | | | 43 | ns | Tamb=-40℃～+125℃; 见图6; VCC=6.0V | 13 |
| OE to Qn enable time | ten | | | 225 | ns | Tamb=-40℃～+125℃; 见图7; VCC=2.0V | 13 |
| OE to Qn enable time | ten | | | 45 | ns | Tamb=-40℃～+125℃; 见图7; VCC=4.5V | 13 |
| OE to Qn enable time | ten | | | 38 | ns | Tamb=-40℃～+125℃; 见图7; VCC=6.0V | 13 |
| OE to Qn disable time | tdis | | | 225 | ns | Tamb=-40℃～+125℃; 见图7; VCC=2.0V | 13 |
| OE to Qn disable time | tdis | | | 45 | ns | Tamb=-40℃～+125℃; 见图7; VCC=4.5V | 13 |
| OE to Qn disable time | tdis | | | 38 | ns | Tamb=-40℃～+125℃; 见图7; VCC=6.0V | 13 |
| Qn output transition time | tt | | | 90 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=2.0V | 13 |
| Qn output transition time | tt | | | 18 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=4.5V | 13 |
| Qn output transition time | tt | | | 15 | ns | Tamb=-40℃～+125℃; Qn output; 见图6; VCC=6.0V | 13 |
| CP pulse width | tW | 120 | | | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=2.0V | 13 |
| CP pulse width | tW | 24 | | | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=4.5V | 13 |
| CP pulse width | tW | 20 | | | ns | Tamb=-40℃～+125℃; CP高电平或低电平; 见图6; VCC=6.0V | 13 |
| Dn to CP setup time | tsu | 90 | | | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 |
| Dn to CP setup time | tsu | 18 | | | ns | Tamb=-40℃～+125℃; 见图6; VCC=4.5V | 13 |
| Dn to CP setup time | tsu | 15 | | | ns | Tamb=-40℃～+125℃; 见图6; VCC=6.0V | 13 |
| Dn to CP hold time | th | 5 | | | ns | Tamb=-40℃～+125℃; 见图6; VCC=2.0V | 13 |
| Maximum clock frequency | fmax | 4 | | | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=2.0V | 13 |
| Maximum clock frequency | fmax | 20 | | | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=4.5V | 13 |
| Maximum clock frequency | fmax | 24 | | | MHz | Tamb=-40℃～+125℃; CP input; 见图6; VCC=6.0V | 13 |
## CAD (KiCad official)
- Symbol: `SN74HC374D`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sn74hc374d-etched.step` / `sn74hc374d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74hc374d.step` / `sn74hc374d.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590923054363197440) (21 pp, sha256 `e6d21ba7a671b3e3`, retrieved 2026-10-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74hc374d-datasheet.pdf)