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SN74HC283N

Public Made by Adom

by adom

lingxingic Specialty Logic, DIP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs sn74hc283n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
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package.json Publish 0.1.0 · Ray 28d ago
page.json sn74hc283n: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 15h ago
README.md sn74hc283n: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
sn74hc283n-etched.fit.json sn74hc283n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74hc283n-etched.glb sn74hc283n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74hc283n-etched.step sn74hc283n: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
sn74hc283n.glb Publish 0.1.0 · Ray 28d ago
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sn74hc283n.step Publish 0.1.0 · Ray 28d ago

SN74HC283N

lingxingic · Specialty Logic · DIP-16

SN74HC283N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S2 output Sum output bit 2. Represents the second bit of the binary sum of A + B + CIN. Push-pull CMOS output.
2 B2 input B operand input bit 2. CMOS-level logic input for the second bit of the B operand.
3 A2 input A operand input bit 2. CMOS-level logic input for the second bit of the A operand.
4 S1 output Sum output bit 1 (LSB). Represents the least-significant bit of the binary sum of A + B + CIN.
5 A1 input A operand input bit 1 (LSB). CMOS-level logic input for the least-significant bit of the A operand.
6 B1 input B operand input bit 1 (LSB). CMOS-level logic input for the least-significant bit of the B operand.
7 CIN input Carry input. Incoming carry bit added to the A+B sum. Tie to GND (active-HIGH operation) or VCC (active-LOW operation) when no carry-in is intended; used when cascading multiple SN74HC283 devices for wider-than-4-bit addition.
8 GND power_in Ground reference (0 V). All input and output voltages are referenced to this pin.
9 COUT output Carry output. Outgoing carry bit resulting from A + B + CIN. Connect to the CIN of the next-higher SN74HC283 stage when cascading to build wider adders.
10 S4 output Sum output bit 4 (MSB). Represents the most-significant bit of the 4-bit binary sum.
11 B4 input B operand input bit 4 (MSB). CMOS-level logic input for the most-significant bit of the B operand.
12 A4 input A operand input bit 4 (MSB). CMOS-level logic input for the most-significant bit of the A operand.
13 S3 output Sum output bit 3. Represents the third bit of the binary sum of A + B + CIN.
14 A3 input A operand input bit 3. CMOS-level logic input for the third bit of the A operand.
15 B3 input B operand input bit 3. CMOS-level logic input for the third bit of the B operand.
16 VCC power_in Positive supply voltage. Operating range 2.0 V to 6.0 V (SN74HC283); absolute maximum 7.0 V. Bypass with a 100 nF ceramic capacitor to GND.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SN74HC283NN(LX)
  • SN74HC283ND(LX)
  • SN74HC283NDR(LX)
  • SN74HC283NPW(LX)

CAD (KiCad official)

  • Symbol: SN74HC283N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc283n-etched.step / sn74hc283n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc283n.step / sn74hc283n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (20 pp, sha256 16ffe47b15cddb94, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF