component

SN74HC21PWR

Public Made by Adom

by adom

Texas Instruments Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sn74hc21pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sn74hc21pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md sn74hc21pwr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sn74hc21pwr-etched.fit.json sn74hc21pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74hc21pwr-etched.glb sn74hc21pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74hc21pwr-etched.step sn74hc21pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74hc21pwr.glb Publish 0.1.0 · Ray
sn74hc21pwr.kicad_mod Publish 0.1.0 · Ray
sn74hc21pwr.kicad_sym Publish 0.1.0 · Ray
sn74hc21pwr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sn74hc21pwr.step Publish 0.1.0 · Ray

SN74HC21PWR

Texas Instruments · Gates · TSSOP-14

SN74HC21PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1, Input A. Standard high-impedance CMOS logic input for the first 4-input AND gate. VIH ≥ 3.15 V @ VCC=4.5 V; VIL ≤ 1.35 V @ VCC=4.5 V.
2 1B input Channel 1, Input B. Standard high-impedance CMOS logic input for the first 4-input AND gate.
3 NC unconnected Not internally connected. Leave floating or tie to a defined level per board practice.
4 1C input Channel 1, Input C. Standard high-impedance CMOS logic input for the first 4-input AND gate.
5 1D input Channel 1, Input D. Standard high-impedance CMOS logic input for the first 4-input AND gate.
6 1Y output Channel 1, Output Y. Balanced CMOS push-pull output; 1Y = 1A · 1B · 1C · 1D. IOH/IOL rated ±4 mA at VCC=4.5 V and ±5.2 mA at VCC=6 V.
7 GND power_in Ground reference (0 V). Common return for VCC supply and all logic inputs/outputs.
8 2Y output Channel 2, Output Y. Balanced CMOS push-pull output; 2Y = 2A · 2B · 2C · 2D.
9 2A input Channel 2, Input A. Standard high-impedance CMOS logic input for the second 4-input AND gate.
10 2B input Channel 2, Input B. Standard high-impedance CMOS logic input for the second 4-input AND gate.
11 NC unconnected Not internally connected. Leave floating or tie to a defined level per board practice.
12 2C input Channel 2, Input C. Standard high-impedance CMOS logic input for the second 4-input AND gate.
13 2D input Channel 2, Input D. Standard high-impedance CMOS logic input for the second 4-input AND gate.
14 VCC power_in Positive supply. Recommended operating range 2 V to 6 V (nominal 5 V); absolute maximum 7 V. Bypass with a ceramic capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • SN74HC21PWR
  • SN74HC21PWRD
  • SN74HC21PWRN
  • SN74HC21PWRNS
  • SN74HC21PWRJ
  • SN74HC21PWRFK

CAD (KiCad official)

  • Symbol: SN74HC21PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74hc21pwr-etched.step / sn74hc21pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc21pwr.step / sn74hc21pwr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74hc21pwr.step 194 KB You want the bare part, or you mark your own boards.
sn74hc21pwr-etched.step 2.3 MB You want the part with SN74HC21PWR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 591 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 d9553773c8d57248, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF