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SN74HC166N

Public Made by Adom

by adom

lingxingic Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74HC166N

lingxingic · Shift Registers · DIP-16

SN74HC166N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DS input Serial data input to the first register stage (Q0), sampled on the LOW-to-HIGH clock edge during a serial shift.
2 D0 input Parallel data input D0, loaded into register Q0 on a LOW-to-HIGH CP edge when PE and CE are LOW.
3 D1 input Parallel data input D1, loaded into register Q1 on a LOW-to-HIGH CP edge when PE and CE are LOW.
4 D2 input Parallel data input D2, loaded into register Q2 on a LOW-to-HIGH CP edge when PE and CE are LOW.
5 D3 input Parallel data input D3, loaded into register Q3 on a LOW-to-HIGH CP edge when PE and CE are LOW.
6 CE input Clock enable input, active LOW; when HIGH the clock is inhibited and the register holds its state.
7 CP input Clock input, triggered on the LOW-to-HIGH edge.
8 GND power_in Ground reference (0 V).
9 MR input Asynchronous master reset, active LOW; clears the register independently of the clock.
10 D4 input Parallel data input D4, loaded into register Q4 on a LOW-to-HIGH CP edge when PE and CE are LOW.
11 D5 input Parallel data input D5, loaded into register Q5 on a LOW-to-HIGH CP edge when PE and CE are LOW.
12 D6 input Parallel data input D6, loaded into register Q6 on a LOW-to-HIGH CP edge when PE and CE are LOW.
13 Q7 output Serial output from the last register stage.
14 D7 input Parallel data input D7, loaded into register Q7 on a LOW-to-HIGH CP edge when PE and CE are LOW.
15 PE input Parallel enable input, active LOW; selects parallel load of D0 to D7 when LOW and serial shift when HIGH.
16 VCC power_in Supply voltage: 2.0 V to 6.0 V for SN74HC166 and 4.5 V to 5.5 V for SN74HCT166 (recommended operating range).

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 6
supply current ICC 50 mA 6
ground current IGND -50 mA 6
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 6
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 6
output current IO -25 25 mA -0.5V < VO < VCC+0.5V 6
storage temperature Tstg -65 150 ℃ 6
soldering temperature TL 245 ℃ 10s, DIP 6
supply voltage VCC 2 5 6 V SN74HC166 6
input voltage VI 0 V SN74HC166 6
output voltage VO 0 V SN74HC166 6
ambient temperature Tamb -40 125 ℃ SN74HC166 6
HIGH-level input voltage VIH 1.5 1.2 V Tamb -40~85℃; VCC 2.0V 7
HIGH-level input voltage VIH 3.15 2.4 V Tamb -40~85℃; VCC 4.5V 7
HIGH-level input voltage VIH 4.2 3.2 V Tamb -40~85℃; VCC 6.0V 7
LOW-level input voltage VIL 0.8 0.5 V Tamb -40~85℃; VCC 2.0V 7
LOW-level input voltage VIL 2.1 1.35 V Tamb -40~85℃; VCC 4.5V 7
LOW-level input voltage VIL 2.8 1.8 V Tamb -40~85℃; VCC 6.0V 7
HIGH-level output voltage VOH 1.9 2 V Tamb -40~85℃; VCC 2.0V; IO=-20uA 7
HIGH-level output voltage VOH 4.4 4.5 V Tamb -40~85℃; VCC 4.5V; IO=-20uA 7
HIGH-level output voltage VOH 5.9 6 V Tamb -40~85℃; VCC 6.0V; IO=-20uA 7
HIGH-level output voltage VOH 3.84 4.32 V Tamb -40~85℃; VCC 4.5V; IO=-4.0mA 7
HIGH-level output voltage VOH 5.34 5.81 V Tamb -40~85℃; VCC 6.0V; IO=-5.2mA 7
LOW-level output voltage VOL 0 0.1 V Tamb -40~85℃; VCC 2.0V; IO=20uA 7
LOW-level output voltage VOL 0.15 0.33 V Tamb -40~85℃; VCC 4.5V; IO=4.0mA 7
LOW-level output voltage VOL 0.16 0.33 V Tamb -40~85℃; VCC 6.0V; IO=5.2mA 7
input leakage current II -1 1 uA Tamb -40~85℃; VCC 6.0V; VI=VCC or GND 7
supply current ICC 80 uA Tamb -40~85℃; VCC 6.0V; VI=VCC or GND; IO=0A 7
HIGH-level input voltage VIH 1.5 V Tamb -40~125℃; VCC 2.0V 8
HIGH-level input voltage VIH 3.15 V Tamb -40~125℃; VCC 4.5V 8
HIGH-level input voltage VIH 4.2 V Tamb -40~125℃; VCC 6.0V 8
LOW-level input voltage VIL 0.5 V Tamb -40~125℃; VCC 2.0V 8
LOW-level input voltage VIL 1.35 V Tamb -40~125℃; VCC 4.5V 8
LOW-level input voltage VIL 1.8 V Tamb -40~125℃; VCC 6.0V 8
HIGH-level output voltage VOH 1.9 V Tamb -40~125℃; VCC 2.0V; IO=-20uA 8
HIGH-level output voltage VOH 4.4 V Tamb -40~125℃; VCC 4.5V; IO=-20uA 8
HIGH-level output voltage VOH 5.9 V Tamb -40~125℃; VCC 6.0V; IO=-20uA 8
HIGH-level output voltage VOH 3.7 V Tamb -40~125℃; VCC 4.5V; IO=-4.0mA 8
HIGH-level output voltage VOH 5.2 V Tamb -40~125℃; VCC 6.0V; IO=-5.2mA 8
LOW-level output voltage VOL 0.1 V Tamb -40~125℃; VCC 2.0V; IO=20uA 8
LOW-level output voltage VOL 0.4 V Tamb -40~125℃; VCC 4.5V; IO=4.0mA 8
input leakage current II -1 1 uA Tamb -40~125℃; VCC 6.0V; VI=VCC or GND 8
supply current ICC 160 uA Tamb -40~125℃; VCC 6.0V; VI=VCC or GND; IO=0A 8
CP to Q7 propagation delay tPLH, tPHL 50 190 ns Tamb -40~85℃; VCC 2.0V; CL=50pF; see Figure 4 9
CP to Q7 propagation delay tPLH, tPHL 18 38 ns Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 4 9
CP to Q7 propagation delay tPLH, tPHL 14 33 ns Tamb -40~85℃; VCC 6.0V; CL=50pF; see Figure 4 9
maximum frequency fmax 4.8 19 MHZ Tamb -40~85℃; VCC 2.0V; CL=50pF; see Figure 4 9
maximum frequency fmax 24 57 MHZ Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 4 9
maximum frequency fmax 28 68 MHZ Tamb -40~85℃; VCC 6.0V; CL=50pF; see Figure 4 9
CP input HIGH or LOW pulse width tw 100 17 ns Tamb -40~85℃; VCC 2.0V; CL=50pF; see Figure 4 9
CP input HIGH or LOW pulse width tw 20 6 ns Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 4 9
CP input HIGH or LOW pulse width tw 17 5 ns Tamb -40~85℃; VCC 6.0V; CL=50pF; see Figure 4 9
Dn, CE to CP set-up time tsu 20 5 ns Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 6 9
MR to Q7 propagation delay 17 40 ns Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 5 9
transition time tTHL, tTLH 7 19 ns Tamb -40~85℃; VCC 4.5V; CL=50pF; see Figure 4 9

CAD (KiCad official)

  • Symbol: SN74HC166N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hc166n-etched.step / sn74hc166n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc166n.step / sn74hc166n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (18 pp, sha256 5bcd211dbd358081, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF