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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	13d ago
viewers	sn74hc165pw: viewers · Ray	13d ago
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page.json	Set visibility: public · Ray	13d ago
README.md	Publish 0.1.0 · Ray	13d ago
sn74hc165pw-etched.glb	sn74hc165pw: factory component page (tier=lcsc) · Ray	13d ago
sn74hc165pw-etched.step	sn74hc165pw: factory component page (tier=lcsc) · Ray	13d ago
sn74hc165pw-hero.glb	sn74hc165pw: hero GLB from the etched model (keeps the MPN mark) · Ray	13d ago
sn74hc165pw-hero.overlay.json	Publish 0.1.0 · Ray	13d ago
sn74hc165pw.glb	Publish 0.1.0 · Ray	13d ago
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sn74hc165pw.kicad_sym	Publish 0.1.0 · Ray	13d ago
sn74hc165pw.lbr	Publish 0.1.0 · Ray	13d ago
sn74hc165pw.step	Publish 0.1.0 · Ray	13d ago

SN74HC165PW

lingxingic · Shift Registers · TSSOP-16

SN74HC165PW from lingxingic, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PL	input	Asynchronous parallel load input, active low: when low, D0 to D7 are loaded asynchronously into the shift register.
2	CP	input	Clock input, triggered on the low-to-high edge; data shifts on the rising edge when CE is low.
3	D4	input	Parallel data input D4 (Dn), loaded into the register when PL is low.
4	D5	input	Parallel data input D5 (Dn), loaded into the register when PL is low.
5	D6	input	Parallel data input D6 (Dn), loaded into the register when PL is low.
6	D7	input	Parallel data input D7 (Dn), loaded into the register when PL is low.
7	Q7N	output	Complementary output of the last register stage (the inverse of Q7, shown with an overbar in the datasheet).
8	GND	power_in	Ground reference, 0 V.
9	Q7	output	Serial output of the last register stage.
10	DS	input	Serial data input, shifted into the register on the CP rising edge when PL is high and CE is low.
11	D0	input	Parallel data input D0 (Dn), loaded into the register when PL is low.
12	D1	input	Parallel data input D1 (Dn), loaded into the register when PL is low.
13	D2	input	Parallel data input D2 (Dn), loaded into the register when PL is low.
14	D3	input	Parallel data input D3 (Dn), loaded into the register when PL is low.
15	CE	input	Clock enable input, active low: when low, data shifts on CP rising edges; a high level disables the CP input.
16	VCC	power_in	Supply voltage; recommended 2.0 V to 6.0 V for SN74HC165 and 4.5 V to 5.5 V for SN74HCT165.

Key specifications

Parameter	Value
Manufacturer	lingxingic
Package	TSSOP-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: SN74HC165PW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: sn74hc165pw-etched.step / sn74hc165pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hc165pw.step / sn74hc165pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: lingxingic datasheet (26 pp, sha256 59e73c3cef5425d2, retrieved 2026-10-09, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF