component
SN74HC165PW
Public Made by Adomby adom
lingxingic Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74HC165PW
lingxingic · Shift Registers · TSSOP-16
SN74HC165PW from lingxingic, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PL | input | Asynchronous parallel load input, active low: when low, D0 to D7 are loaded asynchronously into the shift register. |
| 2 | CP | input | Clock input, triggered on the low-to-high edge; data shifts on the rising edge when CE is low. |
| 3 | D4 | input | Parallel data input D4 (Dn), loaded into the register when PL is low. |
| 4 | D5 | input | Parallel data input D5 (Dn), loaded into the register when PL is low. |
| 5 | D6 | input | Parallel data input D6 (Dn), loaded into the register when PL is low. |
| 6 | D7 | input | Parallel data input D7 (Dn), loaded into the register when PL is low. |
| 7 | Q7N | output | Complementary output of the last register stage (the inverse of Q7, shown with an overbar in the datasheet). |
| 8 | GND | power_in | Ground reference, 0 V. |
| 9 | Q7 | output | Serial output of the last register stage. |
| 10 | DS | input | Serial data input, shifted into the register on the CP rising edge when PL is high and CE is low. |
| 11 | D0 | input | Parallel data input D0 (Dn), loaded into the register when PL is low. |
| 12 | D1 | input | Parallel data input D1 (Dn), loaded into the register when PL is low. |
| 13 | D2 | input | Parallel data input D2 (Dn), loaded into the register when PL is low. |
| 14 | D3 | input | Parallel data input D3 (Dn), loaded into the register when PL is low. |
| 15 | CE | input | Clock enable input, active low: when low, data shifts on CP rising edges; a high level disables the CP input. |
| 16 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for SN74HC165 and 4.5 V to 5.5 V for SN74HCT165. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74HC165PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc165pw-etched.step/sn74hc165pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc165pw.step/sn74hc165pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (26 pp, sha256
59e73c3cef5425d2, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).