component
SN74GTL2003RKSR
Public Made by Adomby adom
Texas Instruments Translators, Level Shifters, DHVQFN-20-EP(2.5x4.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74GTL2003RKSR
Texas Instruments · Translators, Level Shifters · DHVQFN-20-EP(2.5x4.5)
SN74GTL2003RKSR from Texas Instruments, in a DHVQFN-20-EP(2.5x4.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the device. |
| 2 | SREF | passive | Source of the reference transistor; the datasheet recommends VSREF = VDREF - 1.5 V for best level-shifting results, with DC source reference voltage rated 0 V to 5.5 V. |
| 3 | S1 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 4 | S2 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 5 | S3 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 6 | S4 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 7 | S5 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 8 | S6 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 9 | S7 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 10 | S8 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 11 | D8 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 12 | D7 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 13 | D6 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 14 | D5 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 15 | D4 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 16 | D3 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 17 | D2 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 18 | D1 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 19 | DREF | passive | Drain of the reference transistor; tie directly to GREF and pull up to the reference voltage through a 200 kΩ resistor. |
| 20 | GREF | passive | Gate of the reference transistor; tie directly to DREF and pull up to the reference voltage through a 200 kΩ resistor. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DHVQFN-20-EP(2.5x4.5) |
| Category | Logic |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
SN74GTL2003RKSR - Footprint:
Package_DFN_QFN:DHVQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x3mm - 3D model: DHVQFN-20-EP(2.5x4.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sn74gtl2003rksr-etched.step/sn74gtl2003rksr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74gtl2003rksr.step/sn74gtl2003rksr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
f9ee901f4dfeaf97, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74GTL2003RKSR
**Texas Instruments** · Translators, Level Shifters · DHVQFN-20-EP(2.5x4.5)
SN74GTL2003RKSR from Texas Instruments, in a DHVQFN-20-EP(2.5x4.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the device. |
| 2 | SREF | passive | Source of the reference transistor; the datasheet recommends VSREF = VDREF - 1.5 V for best level-shifting results, with DC source reference voltage rated 0 V to 5.5 V. |
| 3 | S1 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 4 | S2 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 5 | S3 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 6 | S4 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 7 | S5 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 8 | S6 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 9 | S7 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 10 | S8 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 11 | D8 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 12 | D7 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 13 | D6 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 14 | D5 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 15 | D4 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 16 | D3 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 17 | D2 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 18 | D1 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |
| 19 | DREF | passive | Drain of the reference transistor; tie directly to GREF and pull up to the reference voltage through a 200 kΩ resistor. |
| 20 | GREF | passive | Gate of the reference transistor; tie directly to DREF and pull up to the reference voltage through a 200 kΩ resistor. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DHVQFN-20-EP(2.5x4.5) |
| Category | Logic |
| Pins | 21 |
## CAD (KiCad official)
- Symbol: `SN74GTL2003RKSR`
- Footprint: `Package_DFN_QFN:DHVQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x3mm`
- 3D model: DHVQFN-20-EP(2.5x4.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `sn74gtl2003rksr-etched.step` / `sn74gtl2003rksr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74gtl2003rksr.step` / `sn74gtl2003rksr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74gtl2003) (30 pp, sha256 `f9ee901f4dfeaf97`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74gtl2003rksr-datasheet.pdf)