component
SN74GTL2003RKSR
Public Made by Adomby adom
Texas Instruments Translators, Level Shifters, DHVQFN-20-EP(2.5x4.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+58@@ -0,0 +1,58 @@+# SN74GTL2003RKSR++**Texas Instruments** · Translators, Level Shifters · DHVQFN-20-EP(2.5x4.5)++SN74GTL2003RKSR from Texas Instruments, in a DHVQFN-20-EP(2.5x4.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground reference pin for the device. |+| 2 | SREF | passive | Source of the reference transistor; the datasheet recommends VSREF = VDREF - 1.5 V for best level-shifting results, with DC source reference voltage rated 0 V to 5.5 V. |+| 3 | S1 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 4 | S2 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 5 | S3 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 6 | S4 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 7 | S5 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 8 | S6 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 9 | S7 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 10 | S8 | bidirectional | LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 11 | D8 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 12 | D7 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 13 | D6 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 14 | D5 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 15 | D4 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 16 | D3 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 17 | D2 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 18 | D1 | bidirectional | GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA. |+| 19 | DREF | passive | Drain of the reference transistor; tie directly to GREF and pull up to the reference voltage through a 200 kΩ resistor. |+| 20 | GREF | passive | Gate of the reference transistor; tie directly to DREF and pull up to the reference voltage through a 200 kΩ resistor. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | DHVQFN-20-EP(2.5x4.5) |+| Category | Logic |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `SN74GTL2003RKSR`+- Footprint: `Package_DFN_QFN:DHVQFN-20-1EP_2.5x4.5mm_P0.5mm_EP1x3mm`+- 3D model: DHVQFN-20-EP(2.5x4.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `sn74gtl2003rksr-etched.step` / `sn74gtl2003rksr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74gtl2003rksr.step` / `sn74gtl2003rksr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74gtl2003) (30 pp, sha256 `f9ee901f4dfeaf97`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74gtl2003rksr-datasheet.pdf)
page.jsonadded+279@@ -0,0 +1,279 @@+{+ "slug": "sn74gtl2003rksr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Translators, Level Shifters, DHVQFN-20-EP(2.5x4.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74gtl2003rksr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74gtl2003rksr.kicad_sym",+ "sn74gtl2003rksr.kicad_mod",+ "sn74gtl2003rksr.glb",+ "sn74gtl2003rksr.step",+ "sn74gtl2003rksr.lbr",+ "docs/hero.png",+ "docs/sn74gtl2003rksr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74gtl2003rksr-hero.glb",+ "sn74gtl2003rksr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74GTL2003RKSR",+ "manufacturer": "Texas Instruments",+ "package": "DHVQFN-20-EP(2.5x4.5)",+ "pin_count": 21,+ "category": "Logic",+ "subcategory": "Translators, Level Shifters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74gtl2003",+ "parts": {+ "symbol": "sn74gtl2003rksr.kicad_sym",+ "footprint": "sn74gtl2003rksr.kicad_mod",+ "model_3d": "sn74gtl2003rksr-hero.glb",+ "model_3d_plain": "sn74gtl2003rksr.glb",+ "model_3d_step": "sn74gtl2003rksr-etched.step",+ "model_3d_step_plain": "sn74gtl2003rksr.step",+ "lbr": "sn74gtl2003rksr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677597",+ "digikey": "296-28686-2-ND",+ "mouser": "595-SN74GTL2003RKSR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T03:07:53Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-28686-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74GTL2003RKSR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin for the device."+ },+ {+ "number": "2",+ "name": "SREF",+ "type": "passive",+ "description": "Source of the reference transistor; the datasheet recommends VSREF = VDREF - 1.5 V for best level-shifting results, with DC source reference voltage rated 0 V to 5.5 V."+ },+ {+ "number": "3",+ "name": "S1",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "4",+ "name": "S2",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "5",+ "name": "S3",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "6",+ "name": "S4",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "7",+ "name": "S5",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "8",+ "name": "S6",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "9",+ "name": "S7",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "10",+ "name": "S8",+ "type": "bidirectional",+ "description": "LVTTL/TTL source port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "11",+ "name": "D8",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "12",+ "name": "D7",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "13",+ "name": "D6",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "14",+ "name": "D5",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "15",+ "name": "D4",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "16",+ "name": "D3",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "17",+ "name": "D2",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "18",+ "name": "D1",+ "type": "bidirectional",+ "description": "GTL drain port; I/O voltage rated 0 V to 5.5 V and pass transistor current up to 64 mA."+ },+ {+ "number": "19",+ "name": "DREF",+ "type": "passive",+ "description": "Drain of the reference transistor; tie directly to GREF and pull up to the reference voltage through a 200 kΩ resistor."+ },+ {+ "number": "20",+ "name": "GREF",+ "type": "passive",+ "description": "Gate of the reference transistor; tie directly to DREF and pull up to the reference voltage through a 200 kΩ resistor."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad is shown in the RKS top-view drawing (figure 5-1) but the datasheet gives it; Package naming differs: the request hint is DHVQFN-20-EP(2.5x4.5), while the datasheet and orderable; Pin types are mapped to KiCad classes: the datasheet lists S and D ports as I/O, mapped to bidirecti",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 10,+ "cost_usd": 0.0602,+ "at": "2026-10-08T03:07:32"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74gtl2003",+ "pages": 30,+ "sha256": "f9ee901f4dfeaf97",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74gtl2003rksr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.52,+ 4.52,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e1f7ec5ea583b9fafae9fe5cdc43f9fcf29761e5801a421f2869bb703b6c3c2e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74gtl2003rksr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 2.52,+ 4.52,+ 0.9+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dbbcab92ddff3ae90bb110f03189b4e4aebf225e98fab7f0a69e887b1b82aa7f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}