# SN74CBTLV3257DR

**Texas Instruments** · Analog Switches, Multiplexers · SOIC-16

SN74CBTLV3257DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | input | Select input that controls the data-flow path of the multiplexer/demultiplexer (S0 in the body text, S in the pin table). |
| 2 | 1B1 | bidirectional | Channel 1 in/out port 1 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 3 | 1B2 | bidirectional | Channel 1 in/out port 2 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 4 | 1A | bidirectional | Channel 1 out/in common port of the FET switch, with rail-to-rail switching on the data I/O ports. |
| 5 | 2B1 | bidirectional | Channel 2 in/out port 1 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 6 | 2B2 | bidirectional | Channel 2 in/out port 2 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 7 | 2A | bidirectional | Channel 2 out/in common port of the FET switch, with rail-to-rail switching on the data I/O ports. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | 3A | bidirectional | Channel 3 out/in common port of the FET switch, with rail-to-rail switching on the data I/O ports. |
| 10 | 3B2 | bidirectional | Channel 3 in/out port 2 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 11 | 3B1 | bidirectional | Channel 3 in/out port 1 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 12 | 4A | bidirectional | Channel 4 out/in common port of the FET switch, with rail-to-rail switching on the data I/O ports. |
| 13 | 4B2 | bidirectional | Channel 4 in/out port 2 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 14 | 4B1 | bidirectional | Channel 4 in/out port 1 of the FET switch, with a 5 Ω switch connection between the two ports. |
| 15 | OE | input | Active-low output enable; the FET multiplexers/demultiplexers are disabled when OE is high, and OE must be tied to VCC through a pullup resistor to hold the high-impedance state during power up or down. |
| 16 | VCC | power_in | Power supply pin; the absolute maximum supply voltage is -0.5 V to 4.6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74CBTLV3257DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74cbtlv3257dr-etched.step` / `sn74cbtlv3257dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74cbtlv3257dr.step` / `sn74cbtlv3257dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74cbtlv3257.pdf) (41 pp, sha256 `ddb143a7fecbb5ee`, retrieved 2026-10-07, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74cbtlv3257dr-datasheet.pdf)