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SN74AVC16827DGGR

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Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-56(6.1x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AVC16827DGGR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-56(6.1x14)

SN74AVC16827DGGR from Texas Instruments, in a TSSOP-56(6.1x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE1 input Active-low output enable for the first 10-bit section; with 1OE2 also low, outputs 1Y1-1Y10 are active, and a high level forces them to high impedance. Tie OE to VCC through a pullup resistor to keep outputs high-impedance during power up or power down.
2 1Y1 tri_state Noninverting 3-state output of channel 1A1; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
3 1Y2 tri_state Noninverting 3-state output of channel 1A2; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
4 GND power_in Ground reference for the device.
5 1Y3 tri_state Noninverting 3-state output of channel 1A3; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
6 1Y4 tri_state Noninverting 3-state output of channel 1A4; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
7 VCC power_in Supply voltage: operable from 1.2 V to 3.6 V and designed specifically for 1.65 V to 3.6 V operation.
8 1Y5 tri_state Noninverting 3-state output of channel 1A5; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
9 1Y6 tri_state Noninverting 3-state output of channel 1A6; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
10 1Y7 tri_state Noninverting 3-state output of channel 1A7; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
11 GND power_in Ground reference for the device.
12 1Y8 tri_state Noninverting 3-state output of channel 1A8; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
13 1Y9 tri_state Noninverting 3-state output of channel 1A9; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
14 1Y10 tri_state Noninverting 3-state output of channel 1A10; active only when 1OE1 and 1OE2 are both low, otherwise high impedance.
15 2Y1 tri_state Noninverting 3-state output of channel 2A1; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
16 2Y2 tri_state Noninverting 3-state output of channel 2A2; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
17 2Y3 tri_state Noninverting 3-state output of channel 2A3; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
18 GND power_in Ground reference for the device.
19 2Y4 tri_state Noninverting 3-state output of channel 2A4; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
20 2Y5 tri_state Noninverting 3-state output of channel 2A5; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
21 2Y6 tri_state Noninverting 3-state output of channel 2A6; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
22 VCC power_in Supply voltage: operable from 1.2 V to 3.6 V and designed specifically for 1.65 V to 3.6 V operation.
23 2Y7 tri_state Noninverting 3-state output of channel 2A7; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
24 2Y8 tri_state Noninverting 3-state output of channel 2A8; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
25 GND power_in Ground reference for the device.
26 2Y9 tri_state Noninverting 3-state output of channel 2A9; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
27 2Y10 tri_state Noninverting 3-state output of channel 2A10; active only when 2OE1 and 2OE2 are both low, otherwise high impedance.
28 2OE1 input Active-low output enable for the second 10-bit section; with 2OE2 also low, outputs 2Y1-2Y10 are active, and a high level forces them to high impedance.
29 2OE2 input Active-low output enable for the second 10-bit section; with 2OE1 also low, outputs 2Y1-2Y10 are active, and a high level forces them to high impedance.
30 2A10 input Data input of channel 2A10 to the noninverting buffer driver, passed to output 2Y10 when enabled.
31 2A9 input Data input of channel 2A9 to the noninverting buffer driver, passed to output 2Y9 when enabled.
32 GND power_in Ground reference for the device.
33 2A8 input Data input of channel 2A8 to the noninverting buffer driver, passed to output 2Y8 when enabled.
34 2A7 input Data input of channel 2A7 to the noninverting buffer driver, passed to output 2Y7 when enabled.
35 VCC power_in Supply voltage: operable from 1.2 V to 3.6 V and designed specifically for 1.65 V to 3.6 V operation.
36 2A6 input Data input of channel 2A6 to the noninverting buffer driver, passed to output 2Y6 when enabled.
37 2A5 input Data input of channel 2A5 to the noninverting buffer driver, passed to output 2Y5 when enabled.
38 2A4 input Data input of channel 2A4 to the noninverting buffer driver, passed to output 2Y4 when enabled.
39 GND power_in Ground reference for the device.
40 2A3 input Data input of channel 2A3 to the noninverting buffer driver, passed to output 2Y3 when enabled.
41 2A2 input Data input of channel 2A2 to the noninverting buffer driver, passed to output 2Y2 when enabled.
42 2A1 input Data input of channel 2A1 to the noninverting buffer driver, passed to output 2Y1 when enabled.
43 1A10 input Data input of channel 1A10 to the noninverting buffer driver, passed to output 1Y10 when enabled.
44 1A9 input Data input of channel 1A9 to the noninverting buffer driver, passed to output 1Y9 when enabled.
45 1A8 input Data input of channel 1A8 to the noninverting buffer driver, passed to output 1Y8 when enabled.
46 GND power_in Ground reference for the device.
47 1A7 input Data input of channel 1A7 to the noninverting buffer driver, passed to output 1Y7 when enabled.
48 1A6 input Data input of channel 1A6 to the noninverting buffer driver, passed to output 1Y6 when enabled.
49 1A5 input Data input of channel 1A5 to the noninverting buffer driver, passed to output 1Y5 when enabled.
50 VCC power_in Supply voltage: operable from 1.2 V to 3.6 V and designed specifically for 1.65 V to 3.6 V operation.
51 1A4 input Data input of channel 1A4 to the noninverting buffer driver, passed to output 1Y4 when enabled.
52 1A3 input Data input of channel 1A3 to the noninverting buffer driver, passed to output 1Y3 when enabled.
53 GND power_in Ground reference for the device.
54 1A2 input Data input of channel 1A2 to the noninverting buffer driver, passed to output 1Y2 when enabled.
55 1A1 input Data input of channel 1A1 to the noninverting buffer driver, passed to output 1Y1 when enabled.
56 1OE2 input Active-low output enable for the first 10-bit section; with 1OE1 also low, outputs 1Y1-1Y10 are active, and a high level forces them to high impedance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-56(6.1x14)
Category Logic
Pins 56

CAD (KiCad official)

  • Symbol: SN74AVC16827DGGR
  • Footprint: Package_SO:TSSOP-56_6.1x14mm_P0.5mm
  • 3D model: TSSOP-56(6.1x14) (KiCad packages3D, STEP)
  • 3D model files: sn74avc16827dggr-etched.step / sn74avc16827dggr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74avc16827dggr.step / sn74avc16827dggr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 2df86698312b9f26, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF