component
SN74AUC1G74DCUR
Public Made by Adomby adom
Texas Instruments Flip Flops, VSSOP-8-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74AUC1G74DCUR
Texas Instruments · Flip Flops · VSSOP-8-0.5mm
SN74AUC1G74DCUR from Texas Instruments, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLK | input | Clock input; data at D is transferred to the outputs on the positive-going edge when PRE and CLR are inactive (high), and inputs are 3.6-V tolerant. |
| 2 | D | input | Data input; data meeting the setup time is transferred to the outputs on the rising clock edge, and it can be changed after the hold-time interval. |
| 3 | Q̅ | output | Complementary flip-flop output with ±8-mA drive at 1.8 V, set low by PRE low and high by CLR low. |
| 4 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±100 mA. |
| 5 | Q | output | True flip-flop output with ±8-mA drive at 1.8 V, set high by PRE low and low by CLR low. |
| 6 | CLR | input | Active-low asynchronous clear that resets Q low regardless of other inputs and overrides PRE when both are low. |
| 7 | PRE | input | Active-low asynchronous preset that sets Q high regardless of the levels of the other inputs. |
| 8 | VCC | power_in | Supply voltage, operational at 0.8 V to 2.7 V and designed for 1.65 V to 1.95 V, with 10 µA max ICC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.5mm |
| Category | Logic |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SN74AUC1G74DCUR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)
- 3D model files:
sn74auc1g74dcur-etched.step/sn74auc1g74dcur-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74auc1g74dcur.step/sn74auc1g74dcur.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
78ef342668836a8c, retrieved 2026-09-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74AUC1G74DCUR
**Texas Instruments** · Flip Flops · VSSOP-8-0.5mm
SN74AUC1G74DCUR from Texas Instruments, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLK | input | Clock input; data at D is transferred to the outputs on the positive-going edge when PRE and CLR are inactive (high), and inputs are 3.6-V tolerant. |
| 2 | D | input | Data input; data meeting the setup time is transferred to the outputs on the rising clock edge, and it can be changed after the hold-time interval. |
| 3 | Q̅ | output | Complementary flip-flop output with ±8-mA drive at 1.8 V, set low by PRE low and high by CLR low. |
| 4 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±100 mA. |
| 5 | Q | output | True flip-flop output with ±8-mA drive at 1.8 V, set high by PRE low and low by CLR low. |
| 6 | CLR | input | Active-low asynchronous clear that resets Q low regardless of other inputs and overrides PRE when both are low. |
| 7 | PRE | input | Active-low asynchronous preset that sets Q high regardless of the levels of the other inputs. |
| 8 | VCC | power_in | Supply voltage, operational at 0.8 V to 2.7 V and designed for 1.65 V to 1.95 V, with 10 µA max ICC. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.5mm |
| Category | Logic |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SN74AUC1G74DCUR`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)
- 3D model files: `sn74auc1g74dcur-etched.step` / `sn74auc1g74dcur-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74auc1g74dcur.step` / `sn74auc1g74dcur.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74auc1g74) (23 pp, sha256 `78ef342668836a8c`, retrieved 2026-09-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74auc1g74dcur-datasheet.pdf)