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SN74AUC1G74DCUR
Public Made by Adomby adom
Texas Instruments Flip Flops, VSSOP-8-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# SN74AUC1G74DCUR++**Texas Instruments** · Flip Flops · VSSOP-8-0.5mm++SN74AUC1G74DCUR from Texas Instruments, in a VSSOP-8-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLK | input | Clock input; data at D is transferred to the outputs on the positive-going edge when PRE and CLR are inactive (high), and inputs are 3.6-V tolerant. |+| 2 | D | input | Data input; data meeting the setup time is transferred to the outputs on the rising clock edge, and it can be changed after the hold-time interval. |+| 3 | Q̅ | output | Complementary flip-flop output with ±8-mA drive at 1.8 V, set low by PRE low and high by CLR low. |+| 4 | GND | power_in | Ground; continuous current through VCC or GND is limited to ±100 mA. |+| 5 | Q | output | True flip-flop output with ±8-mA drive at 1.8 V, set high by PRE low and low by CLR low. |+| 6 | CLR | input | Active-low asynchronous clear that resets Q low regardless of other inputs and overrides PRE when both are low. |+| 7 | PRE | input | Active-low asynchronous preset that sets Q high regardless of the levels of the other inputs. |+| 8 | VCC | power_in | Supply voltage, operational at 0.8 V to 2.7 V and designed for 1.65 V to 1.95 V, with 10 µA max ICC. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-8-0.5mm |+| Category | Logic |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `SN74AUC1G74DCUR`+- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`+- 3D model: VSSOP-8-0.5mm (KiCad packages3D, STEP)+- 3D model files: `sn74auc1g74dcur-etched.step` / `sn74auc1g74dcur-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74auc1g74dcur.step` / `sn74auc1g74dcur.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74auc1g74) (23 pp, sha256 `78ef342668836a8c`, retrieved 2026-09-30, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74auc1g74dcur-datasheet.pdf)
page.jsonadded+157@@ -0,0 +1,157 @@+{+ "slug": "sn74auc1g74dcur",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, VSSOP-8-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74auc1g74dcur",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74auc1g74dcur.kicad_sym",+ "sn74auc1g74dcur.kicad_mod",+ "sn74auc1g74dcur.glb",+ "sn74auc1g74dcur.step",+ "sn74auc1g74dcur.lbr",+ "docs/hero.png",+ "docs/sn74auc1g74dcur-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SN74AUC1G74DCUR",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-8-0.5mm",+ "pin_count": 8,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74auc1g74",+ "parts": {+ "symbol": "sn74auc1g74dcur.kicad_sym",+ "footprint": "sn74auc1g74dcur.kicad_mod",+ "model_3d": "sn74auc1g74dcur-etched.glb",+ "model_3d_plain": "sn74auc1g74dcur.glb",+ "model_3d_step": "sn74auc1g74dcur-etched.step",+ "model_3d_step_plain": "sn74auc1g74dcur.step",+ "lbr": "sn74auc1g74dcur.lbr"+ },+ "distributor_links": {+ "lcsc": "C2677720",+ "digikey": "296-18560-2-ND",+ "mouser": "595-SN74AUC1G74DCUR"+ },+ "distributor_check": {+ "checked_at": "2026-09-30T01:11:26Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-18560-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN74AUC1G74DCUR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; data at D is transferred to the outputs on the positive-going edge when PRE and CLR are inactive (high), and inputs are 3.6-V tolerant."+ },+ {+ "number": "2",+ "name": "D",+ "type": "input",+ "description": "Data input; data meeting the setup time is transferred to the outputs on the rising clock edge, and it can be changed after the hold-time interval."+ },+ {+ "number": "3",+ "name": "Q̅",+ "type": "output",+ "description": "Complementary flip-flop output with ±8-mA drive at 1.8 V, set low by PRE low and high by CLR low."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; continuous current through VCC or GND is limited to ±100 mA."+ },+ {+ "number": "5",+ "name": "Q",+ "type": "output",+ "description": "True flip-flop output with ±8-mA drive at 1.8 V, set high by PRE low and low by CLR low."+ },+ {+ "number": "6",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear that resets Q low regardless of other inputs and overrides PRE when both are low."+ },+ {+ "number": "7",+ "name": "PRE",+ "type": "input",+ "description": "Active-low asynchronous preset that sets Q high regardless of the levels of the other inputs."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, operational at 0.8 V to 2.7 V and designed for 1.65 V to 1.95 V, with 10 µA max ICC."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin assignments for DCU package inferred from spatial layout of PAGE 1 package diagram text; datashe"+ ],+ "pages_sent": 23,+ "cost_usd": 0.1851,+ "at": "2026-09-30T01:11:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74auc1g74",+ "pages": 23,+ "sha256": "78ef342668836a8c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}