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SN74AS109AD

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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AS109AD

Texas Instruments · Flip Flops · SOIC-16

SN74AS109AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear for flip-flop 1; a low level resets 1Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation.
2 1J input J data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises.
3 1K input K data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises.
4 1CLK input Positive-edge clock input for flip-flop 1; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A.
5 1PRE input Active-low asynchronous preset for flip-flop 1; a low level sets 1Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns.
6 1Q output True output of flip-flop 1.
7 1Q̄ output Complementary (inverted) output of flip-flop 1.
8 GND power_in Ground reference for the device.
9 2Q̄ output Complementary (inverted) output of flip-flop 2.
10 2Q output True output of flip-flop 2.
11 2PRE input Active-low asynchronous preset for flip-flop 2; a low level sets 2Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns.
12 2CLK input Positive-edge clock input for flip-flop 2; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A.
13 2K input K data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises.
14 2J input J data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises.
15 2CLR input Active-low asynchronous clear for flip-flop 2; a low level resets 2Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation.
16 VCC power_in Supply voltage; recommended operating range 4.5 V to 5.5 V (nominal 5 V), with an absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74AS109AD
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74as109ad-etched.step / sn74as109ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74as109ad.step / sn74as109ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 16ce99e76112d387, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF