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SN74AS109AD
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Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# SN74AS109AD++**Texas Instruments** · Flip Flops · SOIC-16++SN74AS109AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1CLR | input | Active-low asynchronous clear for flip-flop 1; a low level resets 1Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation. |+| 2 | 1J | input | J data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises. |+| 3 | 1K | input | K data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises. |+| 4 | 1CLK | input | Positive-edge clock input for flip-flop 1; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A. |+| 5 | 1PRE | input | Active-low asynchronous preset for flip-flop 1; a low level sets 1Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns. |+| 6 | 1Q | output | True output of flip-flop 1. |+| 7 | 1Q̄ | output | Complementary (inverted) output of flip-flop 1. |+| 8 | GND | power_in | Ground reference for the device. |+| 9 | 2Q̄ | output | Complementary (inverted) output of flip-flop 2. |+| 10 | 2Q | output | True output of flip-flop 2. |+| 11 | 2PRE | input | Active-low asynchronous preset for flip-flop 2; a low level sets 2Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns. |+| 12 | 2CLK | input | Positive-edge clock input for flip-flop 2; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A. |+| 13 | 2K | input | K data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises. |+| 14 | 2J | input | J data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises. |+| 15 | 2CLR | input | Active-low asynchronous clear for flip-flop 2; a low level resets 2Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation. |+| 16 | VCC | power_in | Supply voltage; recommended operating range 4.5 V to 5.5 V (nominal 5 V), with an absolute maximum of 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74AS109AD`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn74as109ad-etched.step` / `sn74as109ad-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74as109ad.step` / `sn74as109ad.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com.cn/lit/ds/symlink/sn74as109a.pdf) (20 pp, sha256 `16ce99e76112d387`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74as109ad-datasheet.pdf)
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a low level resets 1Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation."+ },+ {+ "number": "2",+ "name": "1J",+ "type": "input",+ "description": "J data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."+ },+ {+ "number": "3",+ "name": "1K",+ "type": "input",+ "description": "K data input of flip-flop 1, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."+ },+ {+ "number": "4",+ "name": "1CLK",+ "type": "input",+ "description": "Positive-edge clock input for flip-flop 1; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A."+ },+ {+ "number": "5",+ "name": "1PRE",+ "type": "input",+ "description": "Active-low asynchronous preset for flip-flop 1; a low level sets 1Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns."+ },+ {+ "number": "6",+ "name": "1Q",+ "type": "output",+ "description": "True output of flip-flop 1."+ },+ {+ "number": "7",+ "name": "1Q̄",+ "type": "output",+ "description": "Complementary (inverted) output of flip-flop 1."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "9",+ "name": "2Q̄",+ "type": "output",+ "description": "Complementary (inverted) output of flip-flop 2."+ },+ {+ "number": "10",+ "name": "2Q",+ "type": "output",+ "description": "True output of flip-flop 2."+ },+ {+ "number": "11",+ "name": "2PRE",+ "type": "input",+ "description": "Active-low asynchronous preset for flip-flop 2; a low level sets 2Q high regardless of the levels of the other inputs, with a minimum low pulse duration of 4 ns."+ },+ {+ "number": "12",+ "name": "2CLK",+ "type": "input",+ "description": "Positive-edge clock input for flip-flop 2; the datasheet specifies a maximum clock frequency of 105 MHz for the SN74AS109A."+ },+ {+ "number": "13",+ "name": "2K",+ "type": "input",+ "description": "K data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."+ },+ {+ "number": "14",+ "name": "2J",+ "type": "input",+ "description": "J data input of flip-flop 2, transferred to the outputs on the positive-going CLK edge when PRE and CLR are inactive (high), with a recommended setup time of 5.5 ns and hold time of 0 ns before and after CLK rises."+ },+ {+ "number": "15",+ "name": "2CLR",+ "type": "input",+ "description": "Active-low asynchronous clear for flip-flop 2; a low level resets 2Q low regardless of the levels of the other inputs, and it must be high for clocked J-K operation."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage; recommended operating range 4.5 V to 5.5 V (nominal 5 V), with an absolute maximum of 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet text extraction drops the overbar on the complementary outputs; names 1Q̄ and 2Q̄ are ; The D (SOIC-16) pinout is taken from the top-view figure shared with the N package, which is labeled"+ ],+ "pages_sent": 20,+ "cost_usd": 0.0901,+ "at": "2026-10-08T14:41:34"+ },+ "datasheet": {+ "url": "https://www.ti.com.cn/lit/ds/symlink/sn74as109a.pdf",+ "pages": 20,+ "sha256": "16ce99e76112d387",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74as109ad.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74as109ad-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fab701c7bb1be6da5f764ae775a5fc2ba98979ed6c77949e136c84b0959f8aee",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}