# SN74AHCT594DR

**Texas Instruments** · Shift Registers · SOIC-16

SN74AHCT594DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Output B, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 2 | QC | output | Output C, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 3 | QD | output | Output D, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 4 | QE | output | Output E, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 5 | QF | output | Output F, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 6 | QG | output | Output G, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 7 | QH | output | Output H, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 8 | GND | power_in | Ground pin. |
| 9 | QH' | output | Serial output QH' (QH inverted) provided for cascading multiple devices; load current should not exceed 25 mA per output (Section 8.2.2). |
| 10 | SRCLR | input | Serial (shift register) clear input; when low it clears the shift register independently of the other inputs (Function Table, Section 7.4). |
| 11 | SRCLK | input | Shift register clock; positive-edge triggered, with the shift register one count ahead of the storage register when both clocks are tied together (Section 7.1). |
| 12 | RCLK | input | Storage register clock; positive-edge triggered, transferring shift register data into the storage register (Section 7.1 and 7.4). |
| 13 | RCLR | input | Storage register clear input; when low it clears the storage register independently of the shift register (Function Table, Section 7.4). |
| 14 | SER | input | Serial data input to the 8-bit shift register; sampled on the SRCLK rising edge (Function Table, Section 7.4). |
| 15 | QA | output | Output A, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |
| 16 | VCC | power_in | Power supply pin; recommended supply range is 4.5 V to 5.5 V (Section 5.3). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74AHCT594DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74ahct594dr-etched.step` / `sn74ahct594dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct594dr.step` / `sn74ahct594dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahct594.pdf) (31 pp, sha256 `fc0a7ee66d7d3d24`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ahct594dr-datasheet.pdf)