component
SN74AHCT594DR
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+52@@ -0,0 +1,52 @@+# SN74AHCT594DR++**Texas Instruments** · Shift Registers · SOIC-16++SN74AHCT594DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | output | Output B, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 2 | QC | output | Output C, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 3 | QD | output | Output D, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 4 | QE | output | Output E, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 5 | QF | output | Output F, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 6 | QG | output | Output G, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 7 | QH | output | Output H, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 8 | GND | power_in | Ground pin. |+| 9 | QH' | output | Serial output QH' (QH inverted) provided for cascading multiple devices; load current should not exceed 25 mA per output (Section 8.2.2). |+| 10 | SRCLR | input | Serial (shift register) clear input; when low it clears the shift register independently of the other inputs (Function Table, Section 7.4). |+| 11 | SRCLK | input | Shift register clock; positive-edge triggered, with the shift register one count ahead of the storage register when both clocks are tied together (Section 7.1). |+| 12 | RCLK | input | Storage register clock; positive-edge triggered, transferring shift register data into the storage register (Section 7.1 and 7.4). |+| 13 | RCLR | input | Storage register clear input; when low it clears the storage register independently of the shift register (Function Table, Section 7.4). |+| 14 | SER | input | Serial data input to the 8-bit shift register; sampled on the SRCLK rising edge (Function Table, Section 7.4). |+| 15 | QA | output | Output A, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2). |+| 16 | VCC | power_in | Power supply pin; recommended supply range is 4.5 V to 5.5 V (Section 5.3). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74AHCT594DR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn74ahct594dr-etched.step` / `sn74ahct594dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahct594dr.step` / `sn74ahct594dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahct594.pdf) (31 pp, sha256 `fc0a7ee66d7d3d24`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ahct594dr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "sn74ahct594dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74ahct594dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74ahct594dr.kicad_sym",+ "sn74ahct594dr.kicad_mod",+ "sn74ahct594dr.glb",+ "sn74ahct594dr.step",+ "sn74ahct594dr.lbr",+ "docs/hero.png",+ "docs/sn74ahct594dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74ahct594dr-hero.glb",+ "sn74ahct594dr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74AHCT594DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74ahct594.pdf",+ "parts": {+ "symbol": "sn74ahct594dr.kicad_sym",+ "footprint": "sn74ahct594dr.kicad_mod",+ "model_3d": "sn74ahct594dr-hero.glb",+ "model_3d_plain": "sn74ahct594dr.glb",+ "model_3d_step": "sn74ahct594dr-etched.step",+ "model_3d_step_plain": "sn74ahct594dr.step",+ "lbr": "sn74ahct594dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2878048",+ "digikey": "296-48660-2-ND",+ "mouser": "595-SN74AHCT594DR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T01:01:54Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-48660-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74AHCT594DR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "QB",+ "type": "output",+ "description": "Output B, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "2",+ "name": "QC",+ "type": "output",+ "description": "Output C, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "3",+ "name": "QD",+ "type": "output",+ "description": "Output D, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "4",+ "name": "QE",+ "type": "output",+ "description": "Output E, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "5",+ "name": "QF",+ "type": "output",+ "description": "Output F, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "6",+ "name": "QG",+ "type": "output",+ "description": "Output G, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "7",+ "name": "QH",+ "type": "output",+ "description": "Output H, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground pin."+ },+ {+ "number": "9",+ "name": "QH'",+ "type": "output",+ "description": "Serial output QH' (QH inverted) provided for cascading multiple devices; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "10",+ "name": "SRCLR",+ "type": "input",+ "description": "Serial (shift register) clear input; when low it clears the shift register independently of the other inputs (Function Table, Section 7.4)."+ },+ {+ "number": "11",+ "name": "SRCLK",+ "type": "input",+ "description": "Shift register clock; positive-edge triggered, with the shift register one count ahead of the storage register when both clocks are tied together (Section 7.1)."+ },+ {+ "number": "12",+ "name": "RCLK",+ "type": "input",+ "description": "Storage register clock; positive-edge triggered, transferring shift register data into the storage register (Section 7.1 and 7.4)."+ },+ {+ "number": "13",+ "name": "RCLR",+ "type": "input",+ "description": "Storage register clear input; when low it clears the storage register independently of the shift register (Function Table, Section 7.4)."+ },+ {+ "number": "14",+ "name": "SER",+ "type": "input",+ "description": "Serial data input to the 8-bit shift register; sampled on the SRCLK rising edge (Function Table, Section 7.4)."+ },+ {+ "number": "15",+ "name": "QA",+ "type": "output",+ "description": "Output A, a parallel output of the 8-bit storage register; load current should not exceed 25 mA per output (Section 8.2.2)."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply pin; recommended supply range is 4.5 V to 5.5 V (Section 5.3)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The TI pin table lists QH' as type 'I' (input), but the datasheet describes QH' as the serial output; The TI pin table gives GND as '—' and VCC as 'Power pin' with no direction. Typed as power_in per th; The pin table in Section 4 is a single table covering all 16-pin package variants (D, DB, N, NS, PW)"+ ],+ "pages_sent": 31,+ "cost_usd": 0.0922,+ "at": "2026-10-08T01:01:33"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74ahct594.pdf",+ "pages": 31,+ "sha256": "fc0a7ee66d7d3d24",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74ahct594dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74ahct594dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e7d03bdfbb16c7ecd760e5c24a04c75f2070cde399e5517bc277d1e70e91e65a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}