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SN74AHCT573DBR

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Texas Instruments Logic ICs, SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74AHCT573DBR

Texas Instruments · Logic ICs · SSOP-20-208mil

SN74AHCT573DBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable; when high, the eight Q outputs are placed in the high-impedance state, and OE should be tied to VCC through a pull-up resistor to keep the outputs high-impedance during power up or power down.
2 1D input Data input to latch 1; while LE is high the 1Q output follows this input, and while LE is low 1Q holds the level present at this input.
3 2D input Data input to latch 2; while LE is high the 2Q output follows this input, and while LE is low 2Q holds the level present at this input.
4 3D input Data input to latch 3; while LE is high the 3Q output follows this input, and while LE is low 3Q holds the level present at this input.
5 4D input Data input to latch 4; while LE is high the 4Q output follows this input, and while LE is low 4Q holds the level present at this input.
6 5D input Data input to latch 5; while LE is high the 5Q output follows this input, and while LE is low 5Q holds the level present at this input.
7 6D input Data input to latch 6; while LE is high the 6Q output follows this input, and while LE is low 6Q holds the level present at this input.
8 7D input Data input to latch 7; while LE is high the 7Q output follows this input, and while LE is low 7Q holds the level present at this input.
9 8D input Data input to latch 8; while LE is high the 8Q output follows this input, and while LE is low 8Q holds the level present at this input.
10 GND power_in Ground reference pin for the device.
11 LE input Latch enable; when high the Q outputs follow the D inputs, and when low the Q outputs are latched at the logic levels of the D inputs.
12 8Q tri_state Output of latch 8, a 3-state output that is high-impedance when OE is high.
13 7Q tri_state Output of latch 7, a 3-state output that is high-impedance when OE is high.
14 6Q tri_state Output of latch 6, a 3-state output that is high-impedance when OE is high.
15 5Q tri_state Output of latch 5, a 3-state output that is high-impedance when OE is high.
16 4Q tri_state Output of latch 4, a 3-state output that is high-impedance when OE is high.
17 3Q tri_state Output of latch 3, a 3-state output that is high-impedance when OE is high.
18 2Q tri_state Output of latch 2, a 3-state output that is high-impedance when OE is high.
19 1Q tri_state Output of latch 1, a 3-state output that is high-impedance when OE is high.
20 VCC power_in Supply pin; the recommended supply range is 4.5 V to 5.5 V, with a 0.1 µF bypass capacitor placed as close to the pin as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-20-208mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 4
High-level input voltage VIH 2 V 4
Low-level input voltage VIL 0.8 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V maximum printed as VCC 4
High-level output current IOH -8 mA 4
Low-level output current IOL 8 mA 4
Input transition rise or fall rate Δt/Δv 20 ns/V 4
Operating free-air temperature TA -40 125 °C SN74AHCT573 4
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range VO -0.5 V maximum printed as VCC + 0.5 V 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -75 75 mA 4
Storage temperature range Tstg -65 150 °C 4
Electrostatic discharge, human body model V(ESD) 0 2000 V HBM, JS-001, all pins 4
Electrostatic discharge, charged device model V(ESD) 0 1000 V CDM, JESD22-C101, all pins 4
High-level output voltage VOH 4.4 V IOH = −50 µA; VCC = 4.5 V 5
High-level output voltage VOH 3.8 V IOH = −8 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.1 V IOL = 50 µA; VCC = 4.5 V 5
Low-level output voltage VOL 0.44 V IOL = 8 mA; VCC = 4.5 V 5
Input leakage current II -1 1 µA 0 V to 5.5 V; VI = 5.5 V or GND 5
Off-state output current IOZ -2.5 2.5 µA VO = VCC or GND; VCC = 5.5 V 5
Quiescent supply current ICC 40 µA VI = VCC or GND; IO = 0; VCC = 5.5 V 5
Additional supply current per input at TTL level ΔICC 1.5 mA One input at 3.4 V; other inputs at VCC or GND; VCC = 5.5 V 5
Input capacitance Ci 10 pF VI = VCC or GND; VCC = 5 V 5
Pulse duration, LE high tw 5 ns VCC = 5 V ± 0.5 V 5
Setup time, data before LE↓ tsu 3.5 ns VCC = 5 V ± 0.5 V 5
Hold time, data after LE↓ th 1.5 ns VCC = 5 V ± 0.5 V 5
Propagation delay D to Q, low-to-high tPLH 1 7 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Propagation delay D to Q, high-to-low tPHL 1 9.5 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Propagation delay LE to Q, low-to-high tPLH 1 8 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Propagation delay LE to Q, high-to-low tPHL 1 9.5 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Enable time OE to Q, high (low-to-high output) tPZH 1 8 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Enable time OE to Q, low tPZL 1 11 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Disable time OE to Q, high tPHZ 1 12 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Disable time OE to Q, low tPLZ 1 10.5 ns CL = 15 pF; VCC = 5 V ± 0.5 V 6
Propagation delay D to Q, low-to-high tPLH 1 8.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Propagation delay D to Q, high-to-low tPHL 1 10.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Propagation delay LE to Q, low-to-high tPLH 1 9.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Propagation delay LE to Q, high-to-low tPHL 1 10.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Enable time OE to Q, high (low-to-high output) tPZH 1 9 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Enable time OE to Q, low tPZL 1 11.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Disable time OE to Q, high tPHZ 1 12.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Disable time OE to Q, low tPLZ 1 11.5 ns CL = 50 pF; VCC = 5 V ± 0.5 V 6
Output skew tsk(o) 1.5 ns CL = 50 pF 6
Junction-to-ambient thermal resistance (DB) RθJA 97.9 °C/W DB package, 20 pins 5
Junction-to-case (top) thermal resistance (DB) RθJC(top) 59.6 °C/W DB package, 20 pins 5
Junction-to-board thermal resistance (DB) RθJB 53.1 °C/W DB package, 20 pins 5
Junction-to-top characterization parameter (DB) ψJT 21.3 °C/W DB package, 20 pins 5
Junction-to-board characterization parameter (DB) ψJB 52.7 °C/W DB package, 20 pins 5

CAD (KiCad official)

  • Symbol: SN74AHCT573DBR
  • Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
  • 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
  • 3D model files: sn74ahct573dbr-etched.step / sn74ahct573dbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ahct573dbr.step / sn74ahct573dbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 6860decf78f52c4f, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF