# SN74AHC273DBR

**Texas Instruments** · Flip Flops · SSOP-20

SN74AHC273DBR from Texas Instruments, in a SSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low direct clear input; when CLR is low, all Q outputs are forced low regardless of CLK and D (Table 1, page 10). |
| 2 | 1Q | output | Output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge and is forced low by CLR. |
| 3 | 1D | input | Data input to flip-flop 1; the value is transferred to 1Q on the positive-going CLK edge when setup time requirements are met. |
| 4 | 2D | input | Data input to flip-flop 2; the value is transferred to 2Q on the positive-going CLK edge when setup time requirements are met. |
| 5 | 2Q | output | Output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge and is forced low by CLR. |
| 6 | 3Q | output | Output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge and is forced low by CLR. |
| 7 | 3D | input | Data input to flip-flop 3; the value is transferred to 3Q on the positive-going CLK edge when setup time requirements are met. |
| 8 | 4D | input | Data input to flip-flop 4; the value is transferred to 4Q on the positive-going CLK edge when setup time requirements are met. |
| 9 | 4Q | output | Output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge and is forced low by CLR. |
| 10 | GND | power_in | Ground pin. |
| 11 | CLK | input | Positive-edge clock input; D has no effect on the outputs while CLK is held high or low. |
| 12 | 5Q | output | Output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge and is forced low by CLR. |
| 13 | 5D | input | Data input to flip-flop 5; the value is transferred to 5Q on the positive-going CLK edge when setup time requirements are met. |
| 14 | 6D | input | Data input to flip-flop 6; the value is transferred to 6Q on the positive-going CLK edge when setup time requirements are met. |
| 15 | 6Q | output | Output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge and is forced low by CLR. |
| 16 | 7Q | output | Output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge and is forced low by CLR. |
| 17 | 7D | input | Data input to flip-flop 7; the value is transferred to 7Q on the positive-going CLK edge when setup time requirements are met. |
| 18 | 8D | input | Data input to flip-flop 8; the value is transferred to 8Q on the positive-going CLK edge when setup time requirements are met. |
| 19 | 8Q | output | Output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge and is forced low by CLR. |
| 20 | VCC | power_in | Supply pin; the datasheet recommends VCC from 2 V to 5.5 V, with bypass capacitors placed close to each VCC pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 |  | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 4 |
| High-level input voltage | VIH | 2.1 |  |  | V | VCC = 3 V | 4 |
| High-level input voltage | VIH | 3.85 |  |  | V | VCC = 5.5 V | 4 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 4 |
| Low-level input voltage | VIL |  |  | 0.9 | V | VCC = 3 V | 4 |
| Low-level input voltage | VIL |  |  | 1.65 | V | VCC = 5.5 V | 4 |
| Input voltage | VI | 0 |  | 5.5 | V |  | 4 |
| Output voltage | VO | 0 |  |  | V | Upper limit printed as VCC | 4 |
| High-level output current | IOH | -50 |  |  | µA | VCC = 2 V | 4 |
| High-level output current | IOH | -4 |  |  | mA | VCC = 3 V ± 0.3 V | 4 |
| High-level output current | IOH | -8 |  |  | mA | VCC = 5.5 V ± 0.5 V | 4 |
| Low-level output current | IOL |  |  | 50 | µA | VCC = 2 V | 4 |
| Low-level output current | IOL |  |  | 4 | mA | VCC = 3 V ± 0.3 V | 4 |
| Low-level output current | IOL |  |  | 8 | mA | VCC = 5.5 V ± 0.5 V | 4 |
| Input transition rise and fall time | Δt/Δv |  |  | 100 | ns/V | VCC = 3 V ± 0.3 V | 4 |
| Input transition rise and fall time | Δt/Δv |  |  | 20 | ns/V | VCC = 5.5 V ± 0.5 V | 4 |
| Operating free-air temperature | TA | -40 |  | 125 | °C | SN74AHC273 | 4 |
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |
| Input voltage range | VI | -0.5 |  | 7 | V |  | 4 |
| Output voltage range | VO | -0.5 |  |  | V | Upper limit printed as VCC + 0.5 | 4 |
| Input clamp current | IIK | -20 |  |  | mA | VI < 0 | 4 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -75 |  | 75 | mA |  | 4 |
| Junction-to-ambient thermal resistance | RθJA |  | 98.7 |  | °C/W | DB (SSOP) package, 20 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 60.4 |  | °C/W | DB (SSOP) package, 20 pins | 5 |
| Junction-to-board thermal resistance | RθJB |  | 56.9 |  | °C/W | DB (SSOP) package, 20 pins | 5 |
| Junction-to-top characterization parameter | ψJT |  | 21.6 |  | °C/W | DB (SSOP) package, 20 pins | 5 |
| Junction-to-board characterization parameter | ψJB |  | 53.5 |  | °C/W | DB (SSOP) package, 20 pins | 5 |
| High-level output voltage | VOH | 1.9 |  |  | V | IOH = -50 µA, VCC = 2 V | 5 |
| High-level output voltage | VOH | 2.9 |  |  | V | IOH = -50 µA, VCC = 3 V | 5 |
| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -50 µA, VCC = 4.5 V | 5 |
| High-level output voltage | VOH | 2.48 |  |  | V | IOH = -4 mA, VCC = 3 V | 5 |
| High-level output voltage | VOH | 3.8 |  |  | V | IOH = -8 mA, VCC = 4.5 V | 5 |
| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50 µA, VCC = 2 V | 5 |
| Low-level output voltage | VOL |  |  | 0.44 | V | IOL = 4 mA, VCC = 3 V | 5 |
| Input leakage current | II | -1 |  | 1 | µA | VI = 5.5 V or GND, VCC = 0 to 5.5 V | 5 |
| Quiescent supply current | ICC |  |  | 40 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 5 |
| Input capacitance | Ci |  | 2.5 | 10 | pF | VI = VCC or GND, VCC = 5 V | 5 |

## CAD (KiCad official)

- Symbol: `SN74AHC273DBR`
- Footprint: `Adom_Gen:Texas_Instruments_SN74`
- 3D model: SSOP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74ahc273dbr-etched.step` / `sn74ahc273dbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahc273dbr.step` / `sn74ahc273dbr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahc273dbr.pdf) (33 pp, sha256 `1669d1f1314e764b`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ahc273dbr-datasheet.pdf)