SN74AHC273DBR

@@ -0,0 +1,103 @@+# SN74AHC273DBR++**Texas Instruments** · Flip Flops · SSOP-20++SN74AHC273DBR from Texas Instruments, in a SSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Active-low direct clear input; when CLR is low, all Q outputs are forced low regardless of CLK and D (Table 1, page 10). |+| 2 | 1Q | output | Output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge and is forced low by CLR. |+| 3 | 1D | input | Data input to flip-flop 1; the value is transferred to 1Q on the positive-going CLK edge when setup time requirements are met. |+| 4 | 2D | input | Data input to flip-flop 2; the value is transferred to 2Q on the positive-going CLK edge when setup time requirements are met. |+| 5 | 2Q | output | Output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge and is forced low by CLR. |+| 6 | 3Q | output | Output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge and is forced low by CLR. |+| 7 | 3D | input | Data input to flip-flop 3; the value is transferred to 3Q on the positive-going CLK edge when setup time requirements are met. |+| 8 | 4D | input | Data input to flip-flop 4; the value is transferred to 4Q on the positive-going CLK edge when setup time requirements are met. |+| 9 | 4Q | output | Output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge and is forced low by CLR. |+| 10 | GND | power_in | Ground pin. |+| 11 | CLK | input | Positive-edge clock input; D has no effect on the outputs while CLK is held high or low. |+| 12 | 5Q | output | Output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge and is forced low by CLR. |+| 13 | 5D | input | Data input to flip-flop 5; the value is transferred to 5Q on the positive-going CLK edge when setup time requirements are met. |+| 14 | 6D | input | Data input to flip-flop 6; the value is transferred to 6Q on the positive-going CLK edge when setup time requirements are met. |+| 15 | 6Q | output | Output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge and is forced low by CLR. |+| 16 | 7Q | output | Output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge and is forced low by CLR. |+| 17 | 7D | input | Data input to flip-flop 7; the value is transferred to 7Q on the positive-going CLK edge when setup time requirements are met. |+| 18 | 8D | input | Data input to flip-flop 8; the value is transferred to 8Q on the positive-going CLK edge when setup time requirements are met. |+| 19 | 8Q | output | Output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge and is forced low by CLR. |+| 20 | VCC | power_in | Supply pin; the datasheet recommends VCC from 2 V to 5.5 V, with bypass capacitors placed close to each VCC pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SSOP-20 |+| Category | Logic |+| Pins | 20 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply voltage | VCC | 2 |  | 5.5 | V |  | 4 |+| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 4 |+| High-level input voltage | VIH | 2.1 |  |  | V | VCC = 3 V | 4 |+| High-level input voltage | VIH | 3.85 |  |  | V | VCC = 5.5 V | 4 |+| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 4 |+| Low-level input voltage | VIL |  |  | 0.9 | V | VCC = 3 V | 4 |+| Low-level input voltage | VIL |  |  | 1.65 | V | VCC = 5.5 V | 4 |+| Input voltage | VI | 0 |  | 5.5 | V |  | 4 |+| Output voltage | VO | 0 |  |  | V | Upper limit printed as VCC | 4 |+| High-level output current | IOH | -50 |  |  | µA | VCC = 2 V | 4 |+| High-level output current | IOH | -4 |  |  | mA | VCC = 3 V ± 0.3 V | 4 |+| High-level output current | IOH | -8 |  |  | mA | VCC = 5.5 V ± 0.5 V | 4 |+| Low-level output current | IOL |  |  | 50 | µA | VCC = 2 V | 4 |+| Low-level output current | IOL |  |  | 4 | mA | VCC = 3 V ± 0.3 V | 4 |+| Low-level output current | IOL |  |  | 8 | mA | VCC = 5.5 V ± 0.5 V | 4 |+| Input transition rise and fall time | Δt/Δv |  |  | 100 | ns/V | VCC = 3 V ± 0.3 V | 4 |+| Input transition rise and fall time | Δt/Δv |  |  | 20 | ns/V | VCC = 5.5 V ± 0.5 V | 4 |+| Operating free-air temperature | TA | -40 |  | 125 | °C | SN74AHC273 | 4 |+| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |+| Input voltage range | VI | -0.5 |  | 7 | V |  | 4 |+| Output voltage range | VO | -0.5 |  |  | V | Upper limit printed as VCC + 0.5 | 4 |+| Input clamp current | IIK | -20 |  |  | mA | VI < 0 | 4 |+| Output clamp current | IOK | -20 |  | 20 | mA | VO < 0 or VO > VCC | 4 |+| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 4 |+| Continuous current through VCC or GND |  | -75 |  | 75 | mA |  | 4 |+| Junction-to-ambient thermal resistance | RθJA |  | 98.7 |  | °C/W | DB (SSOP) package, 20 pins | 5 |+| Junction-to-case (top) thermal resistance | RθJC(top) |  | 60.4 |  | °C/W | DB (SSOP) package, 20 pins | 5 |+| Junction-to-board thermal resistance | RθJB |  | 56.9 |  | °C/W | DB (SSOP) package, 20 pins | 5 |+| Junction-to-top characterization parameter | ψJT |  | 21.6 |  | °C/W | DB (SSOP) package, 20 pins | 5 |+| Junction-to-board characterization parameter | ψJB |  | 53.5 |  | °C/W | DB (SSOP) package, 20 pins | 5 |+| High-level output voltage | VOH | 1.9 |  |  | V | IOH = -50 µA, VCC = 2 V | 5 |+| High-level output voltage | VOH | 2.9 |  |  | V | IOH = -50 µA, VCC = 3 V | 5 |+| High-level output voltage | VOH | 4.4 |  |  | V | IOH = -50 µA, VCC = 4.5 V | 5 |+| High-level output voltage | VOH | 2.48 |  |  | V | IOH = -4 mA, VCC = 3 V | 5 |+| High-level output voltage | VOH | 3.8 |  |  | V | IOH = -8 mA, VCC = 4.5 V | 5 |+| Low-level output voltage | VOL |  |  | 0.1 | V | IOL = 50 µA, VCC = 2 V | 5 |+| Low-level output voltage | VOL |  |  | 0.44 | V | IOL = 4 mA, VCC = 3 V | 5 |+| Input leakage current | II | -1 |  | 1 | µA | VI = 5.5 V or GND, VCC = 0 to 5.5 V | 5 |+| Quiescent supply current | ICC |  |  | 40 | µA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 5 |+| Input capacitance | Ci |  | 2.5 | 10 | pF | VI = VCC or GND, VCC = 5 V | 5 |++## CAD (KiCad official)++- Symbol: `SN74AHC273DBR`+- Footprint: `Adom_Gen:Texas_Instruments_SN74`+- 3D model: SSOP-20 (KiCad packages3D, STEP)+- 3D model files: `sn74ahc273dbr-etched.step` / `sn74ahc273dbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ahc273dbr.step` / `sn74ahc273dbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ahc273dbr.pdf) (33 pp, sha256 `1669d1f1314e764b`, retrieved 2026-10-18, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ahc273dbr-datasheet.pdf)

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when CLR is low, all Q outputs are forced low regardless of CLK and D (Table 1, page 10)."+      },+      {+        "number": "2",+        "name": "1Q",+        "type": "output",+        "description": "Output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "3",+        "name": "1D",+        "type": "input",+        "description": "Data input to flip-flop 1; the value is transferred to 1Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "4",+        "name": "2D",+        "type": "input",+        "description": "Data input to flip-flop 2; the value is transferred to 2Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "5",+        "name": "2Q",+        "type": "output",+        "description": "Output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "6",+        "name": "3Q",+        "type": "output",+        "description": "Output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "7",+        "name": "3D",+        "type": "input",+        "description": "Data input to flip-flop 3; the value is transferred to 3Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "8",+        "name": "4D",+        "type": "input",+        "description": "Data input to flip-flop 4; the value is transferred to 4Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "9",+        "name": "4Q",+        "type": "output",+        "description": "Output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground pin."+      },+      {+        "number": "11",+        "name": "CLK",+        "type": "input",+        "description": "Positive-edge clock input; D has no effect on the outputs while CLK is held high or low."+      },+      {+        "number": "12",+        "name": "5Q",+        "type": "output",+        "description": "Output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "13",+        "name": "5D",+        "type": "input",+        "description": "Data input to flip-flop 5; the value is transferred to 5Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "14",+        "name": "6D",+        "type": "input",+        "description": "Data input to flip-flop 6; the value is transferred to 6Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "15",+        "name": "6Q",+        "type": "output",+        "description": "Output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "16",+        "name": "7Q",+        "type": "output",+        "description": "Output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "17",+        "name": "7D",+        "type": "input",+        "description": "Data input to flip-flop 7; the value is transferred to 7Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "18",+        "name": "8D",+        "type": "input",+        "description": "Data input to flip-flop 8; the value is transferred to 8Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "19",+        "name": "8Q",+        "type": "output",+        "description": "Output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply pin; the datasheet recommends VCC from 2 V to 5.5 V, with bypass capacitors placed close to each VCC pin."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The pin table on page 3 covers all SN74AHC273 packages (DB, DGV, DW, N, NS, PW) with one shared numb; The datasheet gives no per-pin electrical limits. Pin descriptions are built from the pin function t"+        ],+        "pages_sent": 33,+        "cost_usd": 0.0964,+        "at": "2026-10-18T06:20:33"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74ahc273dbr.pdf",+        "pages": 33,+        "sha256": "1669d1f1314e764b",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "sn74ahc273dbr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          5.3,+          10.2,+          1.98+        ],+        "zmin_mm": 0.02,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "6dff36ebd77080baba066b7aca3416ba1a817c310d24eec7f7cd42b41d1e0c8d",+        "checked": "2026-10-18",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "sn74ahc273dbr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          5.3,+          10.2,+          1.98+        ],+        "zmin_mm": 0.02,+        "centre_offset_mm": 0.0,+        "footprint_binding": "identity",+        "sha256": "7f47472372036e3946438d76d06c80c7e25c385ed6d9629d007089c1e549a05f",+        "checked": "2026-10-18",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  }+}

@@ -0,0 +1,269 @@+{+  "slug": "sn74ahc273dbr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Flip Flops, SSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74ahc273dbr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74ahc273dbr.kicad_sym",+    "sn74ahc273dbr.kicad_mod",+    "sn74ahc273dbr.glb",+    "sn74ahc273dbr.step",+    "sn74ahc273dbr.lbr",+    "docs/hero.png",+    "docs/sn74ahc273dbr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "SN74AHC273DBR",+    "manufacturer": "Texas Instruments",+    "package": "SSOP-20",+    "pin_count": 20,+    "category": "Logic",+    "subcategory": "Flip Flops",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74ahc273dbr.pdf",+    "parts": {+      "symbol": "sn74ahc273dbr.kicad_sym",+      "footprint": "sn74ahc273dbr.kicad_mod",+      "model_3d": "sn74ahc273dbr-etched.glb",+      "model_3d_plain": "sn74ahc273dbr.glb",+      "model_3d_step": "sn74ahc273dbr-etched.step",+      "model_3d_step_plain": "sn74ahc273dbr.step",+      "lbr": "sn74ahc273dbr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2877489",+      "digikey": "296-4590-2-ND",+      "mouser": "595-SN74AHC273DBR"+    },+    "distributor_check": {+      "checked_at": "2026-10-18T06:24:14Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-4590-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-SN74AHC273DBR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "CLR",+        "type": "input",+        "description": "Active-low direct clear input; when CLR is low, all Q outputs are forced low regardless of CLK and D (Table 1, page 10)."+      },+      {+        "number": "2",+        "name": "1Q",+        "type": "output",+        "description": "Output of flip-flop 1, which takes the value of 1D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "3",+        "name": "1D",+        "type": "input",+        "description": "Data input to flip-flop 1; the value is transferred to 1Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "4",+        "name": "2D",+        "type": "input",+        "description": "Data input to flip-flop 2; the value is transferred to 2Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "5",+        "name": "2Q",+        "type": "output",+        "description": "Output of flip-flop 2, which takes the value of 2D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "6",+        "name": "3Q",+        "type": "output",+        "description": "Output of flip-flop 3, which takes the value of 3D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "7",+        "name": "3D",+        "type": "input",+        "description": "Data input to flip-flop 3; the value is transferred to 3Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "8",+        "name": "4D",+        "type": "input",+        "description": "Data input to flip-flop 4; the value is transferred to 4Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "9",+        "name": "4Q",+        "type": "output",+        "description": "Output of flip-flop 4, which takes the value of 4D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground pin."+      },+      {+        "number": "11",+        "name": "CLK",+        "type": "input",+        "description": "Positive-edge clock input; D has no effect on the outputs while CLK is held high or low."+      },+      {+        "number": "12",+        "name": "5Q",+        "type": "output",+        "description": "Output of flip-flop 5, which takes the value of 5D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "13",+        "name": "5D",+        "type": "input",+        "description": "Data input to flip-flop 5; the value is transferred to 5Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "14",+        "name": "6D",+        "type": "input",+        "description": "Data input to flip-flop 6; the value is transferred to 6Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "15",+        "name": "6Q",+        "type": "output",+        "description": "Output of flip-flop 6, which takes the value of 6D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "16",+        "name": "7Q",+        "type": "output",+        "description": "Output of flip-flop 7, which takes the value of 7D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "17",+        "name": "7D",+        "type": "input",+        "description": "Data input to flip-flop 7; the value is transferred to 7Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "18",+        "name": "8D",+        "type": "input",+        "description": "Data input to flip-flop 8; the value is transferred to 8Q on the positive-going CLK edge when setup time requirements are met."+      },+      {+        "number": "19",+        "name": "8Q",+        "type": "output",+        "description": "Output of flip-flop 8, which takes the value of 8D on the positive-going CLK edge and is forced low by CLR."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Supply pin; the datasheet recommends VCC from 2 V to 5.5 V, with bypass capacitors placed close to each VCC pin."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The pin table on page 3 covers all SN74AHC273 packages (DB, DGV, DW, N, NS, PW) with one shared numb; The datasheet gives no per-pin electrical limits. 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Generated from the Texas Instruments datasheet land pattern (family R494, spec a51b17ef24)</description>+  <smd name="1" x="-3.6250" y="2.9250" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="2" x="-3.6250" y="2.2750" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="3" x="-3.6250" y="1.6250" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="4" x="-3.6250" y="0.9750" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="5" x="-3.6250" y="0.3250" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="6" x="-3.6250" y="-0.3250" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="7" x="-3.6250" y="-0.9750" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="8" x="-3.6250" y="-1.6250" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="9" x="-3.6250" y="-2.2750" dx="1.1500" dy="0.4000" layer="1" roundness="50"/>+  <smd name="10" x="-3.6250" y="-2.9250" dx="1.1500" dy="0.4000" layer="1" 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</devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>\ No newline at end of file

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