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SN74ACT573NSR

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Texas Instruments Latches, SOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ACT573NSR

Texas Instruments · Latches · SOP-20-208mil

SN74ACT573NSR from Texas Instruments, in a SOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output enable: when OE is high all eight outputs go to high impedance, and OE should be tied to VCC through a pull-up resistor (minimum value set by the driver's current sink capability) to keep outputs in high-Z during power-up or power-down.
2 1D input Data input to latch 1, which is passed to output 1Q while LE is high and held when LE goes low.
3 2D input Data input to latch 2, which is passed to output 2Q while LE is high and held when LE goes low.
4 3D input Data input to latch 3, which is passed to output 3Q while LE is high and held when LE goes low.
5 4D input Data input to latch 4, which is passed to output 4Q while LE is high and held when LE goes low.
6 5D input Data input to latch 5, which is passed to output 5Q while LE is high and held when LE goes low.
7 6D input Data input to latch 6, which is passed to output 6Q while LE is high and held when LE goes low.
8 7D input Data input to latch 7, which is passed to output 7Q while LE is high and held when LE goes low.
9 8D input Data input to latch 8, which is passed to output 8Q while LE is high and held when LE goes low.
10 GND power_in Ground reference pin.
11 LE input Latch enable: when high the Q outputs follow the D inputs, and when low the Q outputs latch the logic levels present at D.
12 8Q tri_state Three-state output of latch 8, which holds the latched level and goes to high impedance when OE is high.
13 7Q tri_state Three-state output of latch 7, which holds the latched level and goes to high impedance when OE is high.
14 6Q tri_state Three-state output of latch 6, which holds the latched level and goes to high impedance when OE is high.
15 5Q tri_state Three-state output of latch 5, which holds the latched level and goes to high impedance when OE is high.
16 4Q tri_state Three-state output of latch 4, which holds the latched level and goes to high impedance when OE is high.
17 3Q tri_state Three-state output of latch 3, which holds the latched level and goes to high impedance when OE is high.
18 2Q tri_state Three-state output of latch 2, which holds the latched level and goes to high impedance when OE is high.
19 1Q tri_state Three-state output of latch 1, which holds the latched level and goes to high impedance when OE is high.
20 VCC power_in Positive supply, specified for 4.5 V to 5.5 V; the datasheet recommends a 0.1 µF bypass capacitor placed as close to the pin as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOP-20-208mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ACT573NSR
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20-208mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: sn74act573nsr-etched.step / sn74act573nsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74act573nsr.step / sn74act573nsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 fe3ab052ad4010d5, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF