SN74ABT821ADWR from Texas Instruments, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Buffered output-enable input places the ten Q outputs in the high-impedance state when high and does not affect the latched data; the outputs are in the high-impedance state during power up or power down when VCC is below 2.1 V.
2	1D	input	Data input to flip-flop 1 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
3	2D	input	Data input to flip-flop 2 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
4	3D	input	Data input to flip-flop 3 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
5	4D	input	Data input to flip-flop 4 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
6	5D	input	Data input to flip-flop 5 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
7	6D	input	Data input to flip-flop 6 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
8	7D	input	Data input to flip-flop 7 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
9	8D	input	Data input to flip-flop 8 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
10	9D	input	Data input to flip-flop 9 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
11	10D	input	Data input to flip-flop 10 that is captured on the positive transition of CLK; the recommended setup time is 2.1 ns and hold time is 1.3 ns.
12	GND	power_in	Ground reference pin for the device; the recommended supply range is 4.5 V to 5.5 V on VCC relative to this pin.
13	CLK	input	Clock input on whose positive transition the ten D inputs are latched and transferred to the Q outputs; maximum clock frequency is 125 MHz with pulse widths of at least 2.9 ns high and 3.8 ns low.
14	10Q	tri_state	Three-state buffered output of flip-flop 10 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
15	9Q	tri_state	Three-state buffered output of flip-flop 9 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
16	8Q	tri_state	Three-state buffered output of flip-flop 8 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
17	7Q	tri_state	Three-state buffered output of flip-flop 7 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
18	6Q	tri_state	Three-state buffered output of flip-flop 6 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
19	5Q	tri_state	Three-state buffered output of flip-flop 5 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
20	4Q	tri_state	Three-state buffered output of flip-flop 4 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
21	3Q	tri_state	Three-state buffered output of flip-flop 3 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
22	2Q	tri_state	Three-state buffered output of flip-flop 2 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
23	1Q	tri_state	Three-state buffered output of flip-flop 1 that drives high-capacitance or low-impedance bus loads with up to 32 mA IOH and 64 mA IOL.
24	VCC	power_in	Supply voltage input with a recommended range of 4.5 V to 5.5 V and an absolute maximum of 7 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-24-300mil
Category	Logic
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	4.5		5.5	V		3
High-level input voltage	VIH	2			V		3
Low-level input voltage	VIL			0.8	V		3
Input voltage	VI	0			V	max printed as VCC	3
High-level output current	IOH	-32			mA		3
Low-level output current	IOL			64	mA		3
Input transition rise or fall rate	∆t/∆v			10	ns/V		3
Power-up ramp rate	∆t/∆VCC			200	µs/V		3
Operating free-air temperature	TA	-40		85	°C		3
Supply voltage range	VCC	-0.5		7	V		3
Input voltage range	VI	-0.5		7	V	see Note 1	3
Voltage applied to any output in high or power-off state	VO	-0.5		5.5	V		3
Current into any output in low state	IO			128	mA	SN74ABT821A	3
Input clamp current	IIK			-18	mA	VI < 0	3
Output clamp current	IOK			-50	mA	VO < 0	3
Storage temperature range	Tstg	-65		150	°C		3
Package thermal impedance	θJA		81		°C/W	DW package	3
Input clamp voltage	VIK			-1.2	V	VCC = 4.5 V, II = -18 mA	4
High-level output voltage	VOH	2.5			V	VCC = 4.5 V, IOH = -3 mA	4
High-level output voltage	VOH	3			V	VCC = 5 V, IOH = -3 mA	4
High-level output voltage	VOH	2			V	VCC = 4.5 V, IOH = -32 mA	4
Low-level output voltage	VOL			0.55	V	VCC = 4.5 V, IOL = 64 mA	4
Input current	II	-1		1	µA	VCC = 0 to 5.5 V, VI = VCC or GND	4
Power-up output high-impedance current	IOZPU	-50		50	µA	VCC = 0 to 2.1 V, VO = 0.5 to 2.7 V, OE = X	4
Power-down output high-impedance current	IOZPD	-50		50	µA	VCC = 2.1 V to 0, VO = 0.5 to 2.7 V, OE = X	4
High-impedance output current high	IOZH			10	µA	VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V	4
High-impedance output current low	IOZL	-10			µA	VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V	4
Power-off input/output current	Ioff	-100		100	µA	VCC = 0, VI or VO ≤ 4.5 V	4
Output high leakage current	ICEX			50	µA	VCC = 5.5 V, VO = 5.5 V, outputs high	4
Short-circuit output current	IO	-180	-100	-50	mA	VCC = 5.5 V, VO = 2.5 V	4
Quiescent supply current, outputs high	ICC		1	250	µA	VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs high	4
Quiescent supply current, outputs low	ICC		24	38	mA	VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs low	4
Quiescent supply current, outputs disabled	ICC		0.5	250	µA	VCC = 5.5 V, IO = 0, VI = VCC or GND, outputs disabled	4
Supply current increase per input at TTL level	∆ICC			1.5	mA	VCC = 5.5 V, one input at 3.4 V, other inputs at VCC or GND	4
Input capacitance	Ci		3.5		pF	VI = 2.5 V or 0.5 V	4
Output capacitance	Co		7.5		pF	VO = 2.5 V or 0.5 V	4
Input hysteresis	Vhys		100		mV		4
Clock frequency	fclock	0		125	MHz		4
Pulse duration CLK high	tw	2.9			ns	CLK high	4
Pulse duration CLK low	tw	3.8			ns	CLK low	4
Setup time, data before CLK↑	tsu	2.1			ns		4
Hold time, data after CLK↑	th	1.3			ns		4
Propagation delay CLK to Q, low-to-high	tPLH	1.6		6.2	ns	CL = 50 pF	5
Propagation delay CLK to Q, high-to-low	tPHL	2.3		6.7	ns	CL = 50 pF	5
Enable time OE to Q, high	tPZH	1		5.8	ns	CL = 50 pF	5
Enable time OE to Q, low	tPZL	2.2		6.3	ns	CL = 50 pF	5
Disable time OE to Q, high	tPHZ	2.7		6.7	ns	CL = 50 pF	5
Disable time OE to Q, low	tPLZ	1.7		6.5	ns	CL = 50 pF	5

CAD (KiCad official)

Symbol: SN74ABT821ADWR
Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
3D model: SOIC-24-300mil (KiCad packages3D, STEP)
3D model files: sn74abt821adwr-etched.step / sn74abt821adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt821adwr.step / sn74abt821adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (15 pp, sha256 16843c4ca7b2e96b, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN74ABT821ADWR

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