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SN74ABT574ADWR

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Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74ABT574ADWR

Texas Instruments · Flip Flops · SOIC-20-300mil

SN74ABT574ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output-enable input; low enables 3-state Q outputs to normal logic state, high places them in high-impedance state.
2 1D input Data input for flip-flop 1; logic level is transferred to output 1Q on positive clock transition.
3 2D input Data input for flip-flop 2; logic level is transferred to output 2Q on positive clock transition.
4 3D input Data input for flip-flop 3; logic level is transferred to output 3Q on positive clock transition.
5 4D input Data input for flip-flop 4; logic level is transferred to output 4Q on positive clock transition.
6 5D input Data input for flip-flop 5; logic level is transferred to output 5Q on positive clock transition.
7 6D input Data input for flip-flop 6; logic level is transferred to output 6Q on positive clock transition.
8 7D input Data input for flip-flop 7; logic level is transferred to output 7Q on positive clock transition.
9 8D input Data input for flip-flop 8; logic level is transferred to output 8Q on positive clock transition.
10 GND power_in Ground; negative supply voltage reference.
11 CLK input Clock input; positive edge triggers transfer of data from D inputs to Q outputs.
12 8Q tri_state 3-state output for flip-flop 8; normal logic state when OE is low, high-impedance when OE is high.
13 7Q tri_state 3-state output for flip-flop 7; normal logic state when OE is low, high-impedance when OE is high.
14 6Q tri_state 3-state output for flip-flop 6; normal logic state when OE is low, high-impedance when OE is high.
15 5Q tri_state 3-state output for flip-flop 5; normal logic state when OE is low, high-impedance when OE is high.
16 4Q tri_state 3-state output for flip-flop 4; normal logic state when OE is low, high-impedance when OE is high.
17 3Q tri_state 3-state output for flip-flop 3; normal logic state when OE is low, high-impedance when OE is high.
18 2Q tri_state 3-state output for flip-flop 2; normal logic state when OE is low, high-impedance when OE is high.
19 1Q tri_state 3-state output for flip-flop 1; normal logic state when OE is low, high-impedance when OE is high.
20 VCC power_in Positive supply voltage; recommended operating voltage range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74ABT574ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74abt574adwr-etched.step / sn74abt574adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74abt574adwr.step / sn74abt574adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 7d8bbb1be5d32de3, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF