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Initial commit: component/sn74abt574adwr

Ray ·b167eae2b8 ·1d ago
2 files changed +286
README.mdadded+56
@@ -0,0 +1,56 @@+# SN74ABT574ADWR++**Texas Instruments** · Flip Flops · SOIC-20-300mil++SN74ABT574ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered output-enable input; low enables 3-state Q outputs to normal logic state, high places them in high-impedance state. |+| 2 | 1D | input | Data input for flip-flop 1; logic level is transferred to output 1Q on positive clock transition. |+| 3 | 2D | input | Data input for flip-flop 2; logic level is transferred to output 2Q on positive clock transition. |+| 4 | 3D | input | Data input for flip-flop 3; logic level is transferred to output 3Q on positive clock transition. |+| 5 | 4D | input | Data input for flip-flop 4; logic level is transferred to output 4Q on positive clock transition. |+| 6 | 5D | input | Data input for flip-flop 5; logic level is transferred to output 5Q on positive clock transition. |+| 7 | 6D | input | Data input for flip-flop 6; logic level is transferred to output 6Q on positive clock transition. |+| 8 | 7D | input | Data input for flip-flop 7; logic level is transferred to output 7Q on positive clock transition. |+| 9 | 8D | input | Data input for flip-flop 8; logic level is transferred to output 8Q on positive clock transition. |+| 10 | GND | power_in | Ground; negative supply voltage reference. |+| 11 | CLK | input | Clock input; positive edge triggers transfer of data from D inputs to Q outputs. |+| 12 | 8Q | tri_state | 3-state output for flip-flop 8; normal logic state when OE is low, high-impedance when OE is high. |+| 13 | 7Q | tri_state | 3-state output for flip-flop 7; normal logic state when OE is low, high-impedance when OE is high. |+| 14 | 6Q | tri_state | 3-state output for flip-flop 6; normal logic state when OE is low, high-impedance when OE is high. |+| 15 | 5Q | tri_state | 3-state output for flip-flop 5; normal logic state when OE is low, high-impedance when OE is high. |+| 16 | 4Q | tri_state | 3-state output for flip-flop 4; normal logic state when OE is low, high-impedance when OE is high. |+| 17 | 3Q | tri_state | 3-state output for flip-flop 3; normal logic state when OE is low, high-impedance when OE is high. |+| 18 | 2Q | tri_state | 3-state output for flip-flop 2; normal logic state when OE is low, high-impedance when OE is high. |+| 19 | 1Q | tri_state | 3-state output for flip-flop 1; normal logic state when OE is low, high-impedance when OE is high. |+| 20 | VCC | power_in | Positive supply voltage; recommended operating voltage range is 4.5 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74ABT574ADWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `sn74abt574adwr-etched.step` / `sn74abt574adwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74abt574adwr.step` / `sn74abt574adwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74abt574a) (26 pp, sha256 `7d8bbb1be5d32de3`, retrieved 2026-10-05, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74abt574adwr-datasheet.pdf)
page.jsonadded+230
@@ -0,0 +1,230 @@+{+  "slug": "sn74abt574adwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74abt574adwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74abt574adwr.kicad_sym",+    "sn74abt574adwr.kicad_mod",+    "sn74abt574adwr.glb",+    "sn74abt574adwr.step",+    "sn74abt574adwr.lbr",+    "docs/hero.png",+    "docs/sn74abt574adwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "sn74abt574adwr-hero.glb",+    "sn74abt574adwr-hero.overlay.json"+  ],+  "component": {+    "mpn": "SN74ABT574ADWR",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-20-300mil",+    "pin_count": 20,+    "category": "Logic",+    "subcategory": "Flip Flops",+    "datasheet": "https://www.ti.com/cn/lit/gpn/sn74abt574a",+    "parts": {+      "symbol": "sn74abt574adwr.kicad_sym",+      "footprint": "sn74abt574adwr.kicad_mod",+      "model_3d": "sn74abt574adwr-hero.glb",+      "model_3d_plain": "sn74abt574adwr.glb",+      "model_3d_step": "sn74abt574adwr-etched.step",+      "model_3d_step_plain": "sn74abt574adwr.step",+      "lbr": "sn74abt574adwr.lbr"+    },+    "distributor_links": {+      "lcsc": 2677761,+      "digikey": "296-1046-2-ND",+      "mouser": "595-SN74ABT574ADWR"+    },+    "distributor_check": {+      "checked_at": "2026-10-05T20:27:33Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-1046-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-SN74ABT574ADWR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "OE",+        "type": "input",+        "description": "Buffered output-enable input; low enables 3-state Q outputs to normal logic state, high places them in high-impedance state."+      },+      {+        "number": "2",+        "name": "1D",+        "type": "input",+        "description": "Data input for flip-flop 1; logic level is transferred to output 1Q on positive clock transition."+      },+      {+        "number": "3",+        "name": "2D",+        "type": "input",+        "description": "Data input for flip-flop 2; logic level is transferred to output 2Q on positive clock transition."+      },+      {+        "number": "4",+        "name": "3D",+        "type": "input",+        "description": "Data input for flip-flop 3; logic level is transferred to output 3Q on positive clock transition."+      },+      {+        "number": "5",+        "name": "4D",+        "type": "input",+        "description": "Data input for flip-flop 4; logic level is transferred to output 4Q on positive clock transition."+      },+      {+        "number": "6",+        "name": "5D",+        "type": "input",+        "description": "Data input for flip-flop 5; logic level is transferred to output 5Q on positive clock transition."+      },+      {+        "number": "7",+        "name": "6D",+        "type": "input",+        "description": "Data input for flip-flop 6; logic level is transferred to output 6Q on positive clock transition."+      },+      {+        "number": "8",+        "name": "7D",+        "type": "input",+        "description": "Data input for flip-flop 7; logic level is transferred to output 7Q on positive clock transition."+      },+      {+        "number": "9",+        "name": "8D",+        "type": "input",+        "description": "Data input for flip-flop 8; logic level is transferred to output 8Q on positive clock transition."+      },+      {+        "number": "10",+        "name": "GND",+        "type": "power_in",+        "description": "Ground; negative supply voltage reference."+      },+      {+        "number": "11",+        "name": "CLK",+        "type": "input",+        "description": "Clock input; positive edge triggers transfer of data from D inputs to Q outputs."+      },+      {+        "number": "12",+        "name": "8Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 8; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "13",+        "name": "7Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 7; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "14",+        "name": "6Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 6; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "15",+        "name": "5Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 5; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "16",+        "name": "4Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 4; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "17",+        "name": "3Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 3; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "18",+        "name": "2Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 2; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "19",+        "name": "1Q",+        "type": "tri_state",+        "description": "3-state output for flip-flop 1; normal logic state when OE is low, high-impedance when OE is high."+      },+      {+        "number": "20",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage; recommended operating voltage range is 4.5 V to 5.5 V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 26,+        "cost_usd": 0.1669,+        "at": "2026-10-05T20:27:17"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/sn74abt574a",+        "pages": 26,+        "sha256": "7d8bbb1be5d32de3",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 20,+        "described": 20,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file