SN65MLVD204BDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	R	output	Receiver output pin.
2	RE	input	Receiver enable pin; High = Disable, Low = Enable.
3	DE	input	Driver enable pin; High = Enable, Low = Disable.
4	D	input	Driver input pin.
5	GND	power_in	Power supply ground.
6	A	bidirectional	Differential I/O bus terminal A; voltage at any bus terminal is limited to -1.4 V to 3.8 V per the recommended operating conditions.
7	B	bidirectional	Differential I/O bus terminal B; voltage at any bus terminal is limited to -1.4 V to 3.8 V per the recommended operating conditions.
8	VCC	power_in	Power supply pin, 3.3 V nominal (3 V to 3.6 V recommended).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Interface ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, VCC	VCC	3	3.3	3.6	V		6
High-level input voltage	VIH	2			V		6
Low-level input voltage	VIL	0		0.8	V		6
Voltage at any bus terminal VA or VB	VA, VB	-1.4		3.8	V		6
Differential load resistance	RL	30		50	Ω		6
Signaling rate	1/tUI			100	Mbps		6
Operating free-air temperature for D package	TA	-40		85	°C		6
Supply voltage range	VCC	-0.5		4	V		6
Input voltage range D, DE, RE		-0.5		4	V		6
Input voltage range A, B		-1.8		4	V		6
Output voltage range R		-0.3		4	V		6
Output voltage range A, B		-1.8		4	V		6
Storage temperature	Tstg	-65		150	°C		6
Supply current, driver only	ICC		13	22	mA	RE and DE at VCC, RL = 50 Ω, All others open	7
Supply current, both disabled	ICC		1	4	mA	RE at VCC, DE at 0 V, RL = No Load, All others open	7
Supply current, both enabled	ICC		16	24	mA	RE at 0 V, DE at VCC, RL = 50 Ω, All others open	7
Supply current, receiver only	ICC		4	13	mA	RE at 0 V, DE at 0 V, All others open	7
Device power dissipation	PD			100	mW	RL = 50 Ω, Input to D is a 50-MHz 50% duty cycle square wave, DE = high, RE = low, TA = 85°C	7
Differential output voltage magnitude	/VAB/	480		650	mV	See Figure 7-2	7
Change in differential output voltage magnitude between logic states	Δ/VAB/	-50		50	mV		7
Steady-state common-mode output voltage	VOS(SS)	0.8		1.2	V	See Figure 7-3	7
Change in steady-state common-mode output voltage between logic states	ΔVOS(SS)	-50		50	mV		7
Peak-to-peak common-mode output voltage	VOS(PP)			150	mV		7
Maximum steady-state open-circuit output voltage A	VA(OC)	0		2.4	V	See Figure 7-7	7
Maximum steady-state open-circuit output voltage B	VB(OC)	0		2.4	V		7
Voltage overshoot, low-to-high level output	VP(H)			1.2	VSS	See Figure 7-5	7
Voltage overshoot, high-to-low level output	VP(L)	-0.2			VSS	See Figure 7-5	7
High-level input current (D, DE)	IIH	0		10	µA	VIH = 2 V to VCC	7
Low-level input current (D, DE)	IIL	0		10	µA	VIL = GND to 0.8 V	7
Differential short-circuit output current magnitude	/IOS/			24	mA	See Figure 7-4	7
High-level output voltage (R)	VOH	2.4			V	IOH = -8 mA	8
Low-level output voltage (R)	VOL			0.4	V	IOL = 8 mA	8
High-level input current (RE)	IIH	-10		0	µA	VIH = 2 V to VCC	8
Low-level input current (RE)	IIL	-10		0	µA	VIL = GND to 0.8 V	8
High-impedance output current (R)	IOZ	-10		15	µA	VO = 0 V or 3.6 V	8
Receiver or transceiver with driver disabled input current IA	IA	0		32	µA	VA = 3.8 V, VB = 1.2 V	8
Receiver or transceiver with driver disabled input current IA	IA	-20		20	µA	VA = 0 V or 2.4 V, VB = 1.2 V	8
Receiver or transceiver with driver disabled input current IA	IA	-32		0	µA	VA = -1.4 V, VB = 1.2 V	8
Receiver or transceiver with driver disabled differential input current (IA, IB)	IAB	-4		4	µA	VA = VB, 1.4 ≤ VA ≤ 3.8 V	8
Transceiver with driver disabled input capacitance CA	CA			12	pF	VB = 1.2 V	8
Transceiver with driver disabled input capacitance CB	CB			12	pF	VA = 1.2 V	8
Transceiver with driver disabled differential input capacitance	CAB			7	pF		8
Transceiver with driver disabled input capacitance balance (CA/CB)	CA/B	0.99		1.01			8
Propagation delay time, low-to-high-level output (driver)	tpLH	2	2.5	3.5	ns	See Figure 7-5	8
Propagation delay time, high-to-low-level output (driver)	tpHL	2	2.5	3.5	ns	See Figure 7-5	8
Differential output signal rise time	tr			2	ns		9
Differential output signal fall time	tf			2	ns		9
Pulse skew (/tpHL, tpLH/)	tsk(p)			150	ps		9
Part-to-part skew	tsk(pp)			0.9	ns		9
Propagation delay time, low-to-high-level output (receiver)	tPLH	2	6	10	ns	CL = 15 pF, See Figure 7-10	9
Propagation delay time, high-to-low-level output (receiver)	tPHL	2	6	10	ns	CL = 15 pF, See Figure 7-10	9
Junction-to-ambient thermal resistance (D SOIC)	RθJA		112.2		°C/W		6
Junction-to-case (top) thermal resistance (D SOIC)	RθJC(top)		56.7		°C/W		6
Junction-to-board thermal resistance (D SOIC)	RθJB		52.8		°C/W		6
Junction-to-top characterization parameter (D SOIC)	ψJT		10.3		°C/W		6
Junction-to-board characterization parameter (D SOIC)	ψJB		52.3		°C/W		6

CAD (KiCad official)

Symbol: SN65MLVD204BDR
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: sn65mlvd204bdr-etched.step / sn65mlvd204bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65mlvd204bdr.step / sn65mlvd204bdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (54 pp, sha256 71566c73a87ab2a8, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

SN65MLVD204BDR

Verified SN65MLVD204BDR

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3D Model

Symbol & Footprint

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Datasheet

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