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SN65LVEP11DGKR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN65LVEP11DGKR
Texas Instruments · Clock Buffers, Drivers, Distributors · VSSOP-8-0.65mm
SN65LVEP11DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q0 | output | True PECL/ECL output of channel 0 (Q0); defaults low when the input is open or at VEE. |
| 2 | Q0̅ | output | Complementary PECL/ECL output of channel 0 (inverted Q0). |
| 3 | Q1 | output | True PECL/ECL output of channel 1 (Q1); defaults low when the input is open or at VEE. |
| 4 | Q1̅ | output | Complementary PECL/ECL output of channel 1 (inverted Q1). |
| 5 | VEE | power_in | Negative supply; 0 V in PECL mode, -2.375 V to -3.8 V in NECL mode. |
| 6 | D̅ | input | Inverting PECL/ECL data input with internal pull-up (37.5 kOhm) and pull-down (75 kOhm) resistors; LVDS compatible. |
| 7 | D | input | Non-inverting PECL/ECL data input with internal 75 kOhm pull-down resistor; LVDS compatible. |
| 8 | VCC | power_in | Positive supply; 2.375 V to 3.8 V in PECL mode, 0 V in NECL mode. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Clock/Timing |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
SN65LVEP11DGKR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
sn65lvep11dgkr-etched.step/sn65lvep11dgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn65lvep11dgkr.step/sn65lvep11dgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
c12189600347f1de, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN65LVEP11DGKR
**Texas Instruments** · Clock Buffers, Drivers, Distributors · VSSOP-8-0.65mm
SN65LVEP11DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q0 | output | True PECL/ECL output of channel 0 (Q0); defaults low when the input is open or at VEE. |
| 2 | Q0̅ | output | Complementary PECL/ECL output of channel 0 (inverted Q0). |
| 3 | Q1 | output | True PECL/ECL output of channel 1 (Q1); defaults low when the input is open or at VEE. |
| 4 | Q1̅ | output | Complementary PECL/ECL output of channel 1 (inverted Q1). |
| 5 | VEE | power_in | Negative supply; 0 V in PECL mode, -2.375 V to -3.8 V in NECL mode. |
| 6 | D̅ | input | Inverting PECL/ECL data input with internal pull-up (37.5 kOhm) and pull-down (75 kOhm) resistors; LVDS compatible. |
| 7 | D | input | Non-inverting PECL/ECL data input with internal 75 kOhm pull-down resistor; LVDS compatible. |
| 8 | VCC | power_in | Positive supply; 2.375 V to 3.8 V in PECL mode, 0 V in NECL mode. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Clock/Timing |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `SN65LVEP11DGKR`
- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`
- 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files: `sn65lvep11dgkr-etched.step` / `sn65lvep11dgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvep11dgkr.step` / `sn65lvep11dgkr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvep11.pdf) (18 pp, sha256 `c12189600347f1de`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn65lvep11dgkr-datasheet.pdf)