component
SN65LVEP11DGKR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# SN65LVEP11DGKR++**Texas Instruments** · Clock Buffers, Drivers, Distributors · VSSOP-8-0.65mm++SN65LVEP11DGKR from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q0 | output | True PECL/ECL output of channel 0 (Q0); defaults low when the input is open or at VEE. |+| 2 | Q0̅ | output | Complementary PECL/ECL output of channel 0 (inverted Q0). |+| 3 | Q1 | output | True PECL/ECL output of channel 1 (Q1); defaults low when the input is open or at VEE. |+| 4 | Q1̅ | output | Complementary PECL/ECL output of channel 1 (inverted Q1). |+| 5 | VEE | power_in | Negative supply; 0 V in PECL mode, -2.375 V to -3.8 V in NECL mode. |+| 6 | D̅ | input | Inverting PECL/ECL data input with internal pull-up (37.5 kOhm) and pull-down (75 kOhm) resistors; LVDS compatible. |+| 7 | D | input | Non-inverting PECL/ECL data input with internal 75 kOhm pull-down resistor; LVDS compatible. |+| 8 | VCC | power_in | Positive supply; 2.375 V to 3.8 V in PECL mode, 0 V in NECL mode. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-8-0.65mm |+| Category | Clock/Timing |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `SN65LVEP11DGKR`+- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`+- 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)+- 3D model files: `sn65lvep11dgkr-etched.step` / `sn65lvep11dgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn65lvep11dgkr.step` / `sn65lvep11dgkr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn65lvep11.pdf) (18 pp, sha256 `c12189600347f1de`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn65lvep11dgkr-datasheet.pdf)
page.jsonadded+200@@ -0,0 +1,200 @@+{+ "slug": "sn65lvep11dgkr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Buffers, Drivers, Distributors, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "sn65lvep11dgkr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn65lvep11dgkr.kicad_sym",+ "sn65lvep11dgkr.kicad_mod",+ "sn65lvep11dgkr.glb",+ "sn65lvep11dgkr.step",+ "sn65lvep11dgkr.lbr",+ "docs/hero.png",+ "docs/sn65lvep11dgkr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn65lvep11dgkr-hero.glb",+ "sn65lvep11dgkr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN65LVEP11DGKR",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-8-0.65mm",+ "pin_count": 8,+ "category": "Clock/Timing",+ "subcategory": "Clock Buffers, Drivers, Distributors",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn65lvep11.pdf",+ "parts": {+ "symbol": "sn65lvep11dgkr.kicad_sym",+ "footprint": "sn65lvep11dgkr.kicad_mod",+ "model_3d": "sn65lvep11dgkr-hero.glb",+ "model_3d_plain": "sn65lvep11dgkr.glb",+ "model_3d_step": "sn65lvep11dgkr-etched.step",+ "model_3d_step_plain": "sn65lvep11dgkr.step",+ "lbr": "sn65lvep11dgkr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2673053",+ "digikey": "296-SN65LVEP11DGKRTR-ND",+ "mouser": "595-SN65LVEP11DGKR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:03:26Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-SN65LVEP11DGKRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-SN65LVEP11DGKR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "Q0",+ "type": "output",+ "description": "True PECL/ECL output of channel 0 (Q0); defaults low when the input is open or at VEE."+ },+ {+ "number": "2",+ "name": "Q0̅",+ "type": "output",+ "description": "Complementary PECL/ECL output of channel 0 (inverted Q0)."+ },+ {+ "number": "3",+ "name": "Q1",+ "type": "output",+ "description": "True PECL/ECL output of channel 1 (Q1); defaults low when the input is open or at VEE."+ },+ {+ "number": "4",+ "name": "Q1̅",+ "type": "output",+ "description": "Complementary PECL/ECL output of channel 1 (inverted Q1)."+ },+ {+ "number": "5",+ "name": "VEE",+ "type": "power_in",+ "description": "Negative supply; 0 V in PECL mode, -2.375 V to -3.8 V in NECL mode."+ },+ {+ "number": "6",+ "name": "D̅",+ "type": "input",+ "description": "Inverting PECL/ECL data input with internal pull-up (37.5 kOhm) and pull-down (75 kOhm) resistors; LVDS compatible."+ },+ {+ "number": "7",+ "name": "D",+ "type": "input",+ "description": "Non-inverting PECL/ECL data input with internal 75 kOhm pull-down resistor; LVDS compatible."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply; 2.375 V to 3.8 V in PECL mode, 0 V in NECL mode."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pinout figure is for the generic SOIC-8/DGK 8-pin diagram. It is not labelled by package, but th; The datasheet gives internal pull-up and pull-down resistor values only as general attributes, not p",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 18,+ "cost_usd": 0.2384,+ "at": "2026-10-08T16:03:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn65lvep11.pdf",+ "pages": 18,+ "sha256": "c12189600347f1de",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn65lvep11dgkr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn65lvep11dgkr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "efaf71a537ae78cf676daf447cba9765b733c99957035a79d106108d6010d32c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}