component
SN65LVDM050QDG4Q1
Public Made by Adomby adom
Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "SN65LVDM050QDG4Q1",
"manufacturer": "Texas Instruments",
"package": "SOIC-16",
"pin_count": 16,
"category": "Interface",
"subcategory": "LVDS ICs",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn65lvdm051-q1",
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"lcsc": "C1545317",
"digikey": "2156-SN65LVDM050QDG4Q1-ND",
"mouser": "595-N65LVDM050QDG4Q1"
},
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"source": "Component Ocean /api/assign-pns",
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"status": "found"
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"pins": [
{
"number": "1",
"name": "1B",
"type": "input",
"description": "Inverting (B) differential input of receiver 1, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe."
},
{
"number": "2",
"name": "1A",
"type": "input",
"description": "Non-inverting (A) differential input of receiver 1, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver."
},
{
"number": "3",
"name": "1R",
"type": "output",
"description": "LVTTL output of receiver 1 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA."
},
{
"number": "4",
"name": "RE",
"type": "input",
"description": "Active-low receiver enable shared by both receivers; a high level places the R outputs in high impedance, with VIH of at least 2 V and VIL of at most 0.8 V."
},
{
"number": "5",
"name": "2R",
"type": "output",
"description": "LVTTL output of receiver 2 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA."
},
{
"number": "6",
"name": "2A",
"type": "input",
"description": "Non-inverting (A) differential input of receiver 2, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver."
},
{
"number": "7",
"name": "2B",
"type": "input",
"description": "Inverting (B) differential input of receiver 2, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Device ground; all voltages except differential I/O bus voltages are referenced to this network ground terminal."
},
{
"number": "9",
"name": "2D",
"type": "input",
"description": "Driver 2 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V."
},
{
"number": "10",
"name": "2Y",
"type": "output",
"description": "Non-inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."
},
{
"number": "11",
"name": "2Z",
"type": "output",
"description": "Inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."
},
{
"number": "12",
"name": "DE",
"type": "input",
"description": "Active-high driver enable shared by both drivers; a low level forces Y and Z of both drivers to high impedance, with VIH of at least 2 V and VIL of at most 0.8 V."
},
{
"number": "13",
"name": "1Z",
"type": "output",
"description": "Inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."
},
{
"number": "14",
"name": "1Y",
"type": "output",
"description": "Non-inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V."
},
{
"number": "15",
"name": "1D",
"type": "input",
"description": "Driver 1 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Single supply pin, specified from 3 V to 3.6 V with 3.3 V nominal."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
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"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The MPN SN65LVDM050QDG4Q1 is listed in the addendum (page 18) as SOIC (D), 16 pins, with part markin; The pin-to-number mapping was reconstructed from the text-extracted diagram labels on page 1, matchi; The 051 diagram on the same page (1DE/2DE, no RE) was not used, since it does not apply to this MPN."
],
"pages_sent": 24,
"cost_usd": 0.0971,
"at": "2026-10-08T14:39:25"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/sn65lvdm051-q1",
"pages": 24,
"sha256": "bbb259bd55ba22b0",
"source_tier": "lcsc"
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"cad": "KiCad official (CC-BY-SA 4.0)",
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"described": 16,
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