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SN65LVDM050QDG4Q1

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDM050QDG4Q1

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDM050QDG4Q1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Inverting (B) differential input of receiver 1, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe.
2 1A input Non-inverting (A) differential input of receiver 1, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver.
3 1R output LVTTL output of receiver 1 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA.
4 RE input Active-low receiver enable shared by both receivers; a high level places the R outputs in high impedance, with VIH of at least 2 V and VIL of at most 0.8 V.
5 2R output LVTTL output of receiver 2 that is high impedance when RE is high, with VOH of at least 2.4 V at −8 mA and VOL of at most 0.4 V at 8 mA.
6 2A input Non-inverting (A) differential input of receiver 2, which detects a 50 mV differential input with up to 1 V ground potential difference between transmitter and receiver.
7 2B input Inverting (B) differential input of receiver 2, which resolves a differential input of ±50 mV (VIT+ = 50 mV, VIT− = −50 mV) with open-circuit fail-safe.
8 GND power_in Device ground; all voltages except differential I/O bus voltages are referenced to this network ground terminal.
9 2D input Driver 2 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V.
10 2Y output Non-inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V.
11 2Z output Inverting LVDS output of driver 2, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V.
12 DE input Active-high driver enable shared by both drivers; a low level forces Y and Z of both drivers to high impedance, with VIH of at least 2 V and VIL of at most 0.8 V.
13 1Z output Inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V.
14 1Y output Non-inverting LVDS output of driver 1, providing a differential output of at least 247 mV across a 50 Ω load and high impedance when disabled or when VCC is below 1.5 V.
15 1D input Driver 1 LVTTL data input, 5 V tolerant, with VIH of at least 2 V and VIL of at most 0.8 V.
16 VCC power_in Single supply pin, specified from 3 V to 3.6 V with 3.3 V nominal.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDM050QDG4Q1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdm050qdg4q1-etched.step / sn65lvdm050qdg4q1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdm050qdg4q1.step / sn65lvdm050qdg4q1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 bbb259bd55ba22b0, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF