component
SN65LV1224BRHBT
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, VQFN-32-EP(5x5). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "SN65LV1224BRHBT",
"manufacturer": "Texas Instruments",
"package": "VQFN-32-EP(5x5)",
"pin_count": 32,
"category": "Global Sourcing Parts",
"subcategory": "Global Sourcing Parts",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn65lv1224b",
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"pins": [
{
"number": "1",
"name": "AVCC",
"type": "power_in",
"description": "Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V."
},
{
"number": "2",
"name": "RI+",
"type": "input",
"description": "Noninverting LVDS serial data input with an input threshold sensitivity of ±50 mV."
},
{
"number": "3",
"name": "RI-",
"type": "input",
"description": "Inverting LVDS serial data input with an input threshold sensitivity of ±50 mV."
},
{
"number": "4",
"name": "PWRDN",
"type": "input",
"description": "LVTTL input; driving it low turns off the PLL and puts the outputs into high impedance (low-power mode), and it must be held low for a minimum of 16 ns to initiate power down."
},
{
"number": "5",
"name": "REN",
"type": "input",
"description": "LVTTL input; driving it low places ROUT0-ROUT9 and RCLK into the high-impedance state."
},
{
"number": "6",
"name": "RCLK",
"type": "output",
"description": "LVTTL recovered clock output used to strobe ROUTx data."
},
{
"number": "7",
"name": "LOCK",
"type": "output",
"description": "LVTTL output that goes low when the deserializer PLL locks onto the embedded clock edge."
},
{
"number": "8",
"name": "AVCC",
"type": "power_in",
"description": "Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V."
},
{
"number": "9",
"name": "AVCC",
"type": "power_in",
"description": "Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V."
},
{
"number": "10",
"name": "AGND",
"type": "power_in",
"description": "Analog circuit ground for the PLL and analog circuits."
},
{
"number": "11",
"name": "AGND",
"type": "power_in",
"description": "Analog circuit ground for the PLL and analog circuits."
},
{
"number": "12",
"name": "DGND",
"type": "power_in",
"description": "Digital circuit ground."
},
{
"number": "13",
"name": "DGND",
"type": "power_in",
"description": "Digital circuit ground."
},
{
"number": "14",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "15",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "16",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "17",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "18",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "19",
"name": "DGND",
"type": "power_in",
"description": "Digital circuit ground."
},
{
"number": "20",
"name": "DVCC",
"type": "power_in",
"description": "Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V."
},
{
"number": "21",
"name": "DGND",
"type": "power_in",
"description": "Digital circuit ground."
},
{
"number": "22",
"name": "DVCC",
"type": "power_in",
"description": "Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V."
},
{
"number": "23",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "24",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "25",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "26",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "27",
"name": "ROUT0–ROUT9",
"type": "output",
"description": "LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table."
},
{
"number": "28",
"name": "AGND",
"type": "power_in",
"description": "Analog circuit ground for the PLL and analog circuits."
},
{
"number": "29",
"name": "AGND",
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"description": "Analog circuit ground for the PLL and analog circuits."
},
{
"number": "30",
"name": "AGND",
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"description": "Analog circuit ground for the PLL and analog circuits."
},
{
"number": "31",
"name": "RCLK_R/F",
"type": "input",
"description": "LVTTL input; low selects the RCLK falling-edge data strobe and high selects the rising-edge strobe."
},
{
"number": "32",
"name": "REFCLK",
"type": "input",
"description": "LVTTL input that supplies the reference clock for the internal PLL frequency."
}
],
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