component

SN65LV1224BRHBT

Public Made by Adom

by adom

Texas Instruments Global Sourcing Parts, VQFN-32-EP(5x5). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

componentglobal sourcing partssn65lv1224brhbtfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers sn65lv1224brhbt: viewers · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt-etched.glb Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt-etched.step sn65lv1224brhbt: factory component page (tier=lcsc) · Ray 13d ago
sn65lv1224brhbt-hero.glb sn65lv1224brhbt: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
sn65lv1224brhbt-hero.overlay.json Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt.glb Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt.kicad_mod Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt.kicad_sym Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt.lbr Publish 0.1.0 · Ray 13d ago
sn65lv1224brhbt.step Publish 0.1.0 · Ray 13d ago

SN65LV1224BRHBT

Texas Instruments · Global Sourcing Parts · VQFN-32-EP(5x5)

SN65LV1224BRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVCC power_in Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V.
2 RI+ input Noninverting LVDS serial data input with an input threshold sensitivity of ±50 mV.
3 RI- input Inverting LVDS serial data input with an input threshold sensitivity of ±50 mV.
4 PWRDN input LVTTL input; driving it low turns off the PLL and puts the outputs into high impedance (low-power mode), and it must be held low for a minimum of 16 ns to initiate power down.
5 REN input LVTTL input; driving it low places ROUT0-ROUT9 and RCLK into the high-impedance state.
6 RCLK output LVTTL recovered clock output used to strobe ROUTx data.
7 LOCK output LVTTL output that goes low when the deserializer PLL locks onto the embedded clock edge.
8 AVCC power_in Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V.
9 AVCC power_in Analog circuit power supply for the PLL and analog circuits; DVCC and AVCC must each be within 3 V to 3.6 V.
10 AGND power_in Analog circuit ground for the PLL and analog circuits.
11 AGND power_in Analog circuit ground for the PLL and analog circuits.
12 DGND power_in Digital circuit ground.
13 DGND power_in Digital circuit ground.
14 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
15 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
16 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
17 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
18 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
19 DGND power_in Digital circuit ground.
20 DVCC power_in Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V.
21 DGND power_in Digital circuit ground.
22 DVCC power_in Digital circuit power supply; DVCC and AVCC must each be within 3 V to 3.6 V.
23 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
24 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
25 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
26 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
27 ROUT0-ROUT9 output LVTTL parallel data output; this pin is one of the ROUT0-ROUT9 group (pins 14-18 and 23-27), with the per-bit assignment not stated in the table.
28 AGND power_in Analog circuit ground for the PLL and analog circuits.
29 AGND power_in Analog circuit ground for the PLL and analog circuits.
30 AGND power_in Analog circuit ground for the PLL and analog circuits.
31 RCLK_R/F input LVTTL input; low selects the RCLK falling-edge data strobe and high selects the rising-edge strobe.
32 REFCLK input LVTTL input that supplies the reference clock for the internal PLL frequency.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Global Sourcing Parts
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3 3.3 3.6 V DVCC and AVCC each within 3 V to 3.6 V (datasheet note 1) 7
Receiver input voltage range 0 2.4 V 7
Supply noise voltage 100 mVPP 7
Operating free-air temperature TA -40 25 °C 7
Supply voltage to GND VCC -0.3 4 V VCC to GND 7
LVTTL input voltage -0.3 V Printed maximum is (VCC + 0.3 V) 7
LVTTL output voltage -0.3 V Printed maximum is (VCC + 0.3 V) 7
LVDS receiver input voltage -0.3 3.9 V 7
Electrostatic discharge HBM 6 kV HBM, up to 7
Electrostatic discharge MM 200 V MM, up to 7
Junction temperature 150 °C 7
Storage temperature -65 150 °C 7
RHB package maximum power dissipation 2.85 W RHB package, TA = 25°C 7
RHB package derating 23.6 mW/°C RHB package, above 25°C 7
High-level input voltage (deserializer LVCMOS) VIH 2 V 8
Low-level input voltage (deserializer LVCMOS) VIL 0.8 V 8
Input clamp voltage (deserializer LVCMOS) VCL -0.62 -1.5 V ICL = −18 mA 8
Input current (pull-up and pull-down resistors on inputs) IIN -200 200 μA VIN = 0 V or 3.6 V 8
High-level output voltage VOH 2.2 3 V IOH = −5 mA 8
Low-level output voltage VOL 0.25 0.5 V IOL = 5 mA 8
Output short-circuit current IOS -15 -47 -85 mA VOUT = 0 V 8
High-impedance output current IOZ -10 10 μA PWRDN or REN = 0.8 V, VOUT = 0 V or VCC 8
Differential threshold high voltage VTH 50 mV VCM = 1.1 V 8
Differential threshold low voltage VTL -50 mV 8
Input current (RI+ and RI-), high IIN -10 15 μA VIN = 2.4 V, VCC = 3.6 V or 0 V 8
Input current (RI+ and RI-), low IIN -10 0.05 10 μA VIN = 0 V, VCC = 3.6 V or 0 V 8
Deserializer supply current, worst case f = 10 MHz ICCR 15 35 mA CL = 15 pF, See Figure 5, worst case, f = 10 MHz 8
Deserializer supply current, worst case f = 66 MHz ICCR 80 95 mA CL = 15 pF, See Figure 5, worst case, f = 66 MHz 8
Deserializer supply current, power down ICCXR 0.36 1 mA PWRDN = 0.8 V, REN = 0.8 V 8
REFCLK frequency tolerance -100 100 ppm 10
REFCLK period tRFCP 15.15 100 ns 10
REFCLK duty cycle tRFDC 30 50 70 % 10
REFCLK transition time tt(RF) 3 6 ns 10
Receiver out clock period RCLK t(RCP) 15.15 100 ns t(RCP) = t(TCP), See Figure 13 11
CMOS/TTL low-to-high transition time (ROUT0-ROUT9, LOCK, RCLK) tTLH(C) 1.2 2.5 ns CL = 15 pF, See Figure 7 11
CMOS/TTL high-to-low transition time (ROUT0-ROUT9, LOCK, RCLK) tTHL(C) 1.1 2.5 ns CL = 15 pF, See Figure 7 11
Deserializer delay at 10 MHz (offset added to 1.75×t(RCP)) td(D) 4.2 12.6 ns Room temperature, 3.3 V, 10 MHz, See Figure 14 11
Deserializer delay at 66 MHz (offset added to 1.75×t(RCP)) td(D) 7.4 9.7 ns Room temperature, 3.3 V, 66 MHz, See Figure 14 11
RCLK duty cycle t(RDC) 40 50 60 % 11
High-to-high impedance state delay td(HZ) 6.5 8 ns ROUT0-ROUT9, See Figure 16 11
Low-to-high impedance state delay td(LZ) 4.7 8 ns ROUT0-ROUT9, See Figure 16 11
High-impedance state to high delay td(HR) 5.3 8 ns ROUT0-ROUT9, See Figure 16 11
High-impedance state to low delay td(ZL) 4.7 8 ns ROUT0-ROUT9, See Figure 16 11
Input single-ended capacitance (nominal) CI 0.5 pF 8
Input single-ended capacitance tolerance CI -20 20 % 8

CAD (KiCad official)

  • Symbol: SN65LV1224BRHBT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: sn65lv1224brhbt-etched.step / sn65lv1224brhbt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lv1224brhbt.step / sn65lv1224brhbt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 4bd91afc862e7bca, retrieved 2026-10-20, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF