SN65LV1023AMDBREP

{
  "slug": "sn65lv1023amdbrep",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Serializers, Deserializers, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "sn65lv1023amdbrep",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
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    "path": "docs/hero.png"
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    "README.md",
    "sn65lv1023amdbrep.kicad_sym",
    "sn65lv1023amdbrep.kicad_mod",
    "sn65lv1023amdbrep.glb",
    "sn65lv1023amdbrep.step",
    "sn65lv1023amdbrep.lbr",
    "docs/hero.png",
    "docs/sn65lv1023amdbrep-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
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    "sn65lv1023amdbrep-hero.overlay.json"
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  "component": {
    "mpn": "SN65LV1023AMDBREP",
    "manufacturer": "Texas Instruments",
    "package": "SSOP-28-208mil",
    "pin_count": 28,
    "category": "Interface",
    "subcategory": "Serializers, Deserializers",
    "datasheet": "https://www.ti.com/cn/lit/gpn/sn65lv1023a-ep",
    "parts": {
      "symbol": "sn65lv1023amdbrep.kicad_sym",
      "footprint": "sn65lv1023amdbrep.kicad_mod",
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      "lbr": "sn65lv1023amdbrep.lbr"
    },
    "distributor_links": {
      "lcsc": "C2873138",
      "digikey": "296-21243-2-ND",
      "mouser": "595-65LV1023AMDBREP"
    },
    "distributor_check": {
      "checked_at": "2026-10-11T17:12:31Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-21243-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-65LV1023AMDBREP",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "SYNC1",
        "type": "input",
        "description": "LVTTL logic input; SYNC1 and SYNC2 are ORed, and when either is high for 6 TCLK cycles the serializer sends a minimum of 1026 SYNC patterns, with transmission continuing while SYNC stays asserted."
      },
      {
        "number": "2",
        "name": "SYNC2",
        "type": "input",
        "description": "LVTTL logic input ORed with SYNC1; when high for 6 TCLK cycles it initiates a minimum of 1026 SYNC pattern transmissions, and repeats if SYNC is held high longer than 6 cycles."
      },
      {
        "number": "3",
        "name": "DIN0",
        "type": "input",
        "description": "Parallel LVTTL data input bit 0, latched by TCLK."
      },
      {
        "number": "4",
        "name": "DIN1",
        "type": "input",
        "description": "Parallel LVTTL data input bit 1, latched by TCLK."
      },
      {
        "number": "5",
        "name": "DIN2",
        "type": "input",
        "description": "Parallel LVTTL data input bit 2, latched by TCLK."
      },
      {
        "number": "6",
        "name": "DIN3",
        "type": "input",
        "description": "Parallel LVTTL data input bit 3, latched by TCLK."
      },
      {
        "number": "7",
        "name": "DIN4",
        "type": "input",
        "description": "Parallel LVTTL data input bit 4, latched by TCLK."
      },
      {
        "number": "8",
        "name": "DIN5",
        "type": "input",
        "description": "Parallel LVTTL data input bit 5, latched by TCLK."
      },
      {
        "number": "9",
        "name": "DIN6",
        "type": "input",
        "description": "Parallel LVTTL data input bit 6, latched by TCLK."
      },
      {
        "number": "10",
        "name": "DIN7",
        "type": "input",
        "description": "Parallel LVTTL data input bit 7, latched by TCLK."
      },
      {
        "number": "11",
        "name": "DIN8",
        "type": "input",
        "description": "Parallel LVTTL data input bit 8, latched by TCLK."
      },
      {
        "number": "12",
        "name": "DIN9",
        "type": "input",
        "description": "Parallel LVTTL data input bit 9, latched by TCLK."
      },
      {
        "number": "13",
        "name": "TCLK_R/F",
        "type": "input",
        "description": "LVTTL logic input; low selects a TCLK falling-edge data strobe and high selects a TCLK rising-edge data strobe."
      },
      {
        "number": "14",
        "name": "TCLK",
        "type": "input",
        "description": "LVTTL-level reference clock input accepting 10 MHz to 66 MHz; it strobes parallel data into the input latch and provides the PLL reference frequency."
      },
      {
        "number": "15",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital circuit ground."
      },
      {
        "number": "16",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital circuit ground."
      },
      {
        "number": "17",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog circuit power supply for the PLL and analog circuits."
      },
      {
        "number": "18",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog circuit ground for the PLL and analog circuits."
      },
      {
        "number": "19",
        "name": "DEN",
        "type": "input",
        "description": "LVTTL logic input; high enables the serial data output, and driving it low puts the LVDS output into the high-impedance state."
      },
      {
        "number": "20",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog circuit ground for the PLL and analog circuits."
      },
      {
        "number": "21",
        "name": "DO-",
        "type": "output",
        "description": "Inverting LVDS differential serial data output."
      },
      {
        "number": "22",
        "name": "DO+",
        "type": "output",
        "description": "Noninverting LVDS differential serial data output."
      },
      {
        "number": "23",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog circuit ground for the PLL and analog circuits."
      },
      {
        "number": "24",
        "name": "PWRDN",
        "type": "input",
        "description": "LVTTL logic input; driving it low turns off the PLL, places the outputs in high-impedance, and enters a low-power mode."
      },
      {
        "number": "25",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog circuit ground for the PLL and analog circuits."
      },
      {
        "number": "26",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog circuit power supply for the PLL and analog circuits."
      },
      {
        "number": "27",
        "name": "DVCC",
        "type": "power_in",
        "description": "Digital circuit power supply."
      },
      {
        "number": "28",
        "name": "DVCC",
        "type": "power_in",
        "description": "Digital circuit power supply."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The SN65LV1023AMDBREP is the serializer; the datasheet covers the SN65LV1023A (serializer) and SN65L; The DB (SSOP-28) package is the only package listed for this orderable part (page 1 ordering table a; The page 2 pin-diagram text is scrambled in extraction, so pin-to-name mapping was taken from the Te",
          "4/28 pins cited to the wrong page (name found elsewhere): ['5:DIN2@p7', '6:DIN3@p7', '9:DIN6@p7', '10:DIN7@p7']"
        ],
        "pages_sent": 11,
        "cost_usd": 0.0701,
        "at": "2026-10-11T17:12:11"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/sn65lv1023a-ep",
        "pages": 29,
        "sha256": "2c0fadd4093ca5b1",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 28,
        "described": 28,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
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        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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        "sha256": "2cbf7be400efdfe2f39935304ae59a5768e71a3801d3b65b7503c66e0ddef37e",
        "checked": "2026-10-11",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  }
}