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SN65LV1023AMDBREP

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Texas Instruments Serializers, Deserializers, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN65LV1023AMDBREP

Texas Instruments · Serializers, Deserializers · SSOP-28-208mil

SN65LV1023AMDBREP from Texas Instruments, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC1 input LVTTL logic input; SYNC1 and SYNC2 are ORed, and when either is high for 6 TCLK cycles the serializer sends a minimum of 1026 SYNC patterns, with transmission continuing while SYNC stays asserted.
2 SYNC2 input LVTTL logic input ORed with SYNC1; when high for 6 TCLK cycles it initiates a minimum of 1026 SYNC pattern transmissions, and repeats if SYNC is held high longer than 6 cycles.
3 DIN0 input Parallel LVTTL data input bit 0, latched by TCLK.
4 DIN1 input Parallel LVTTL data input bit 1, latched by TCLK.
5 DIN2 input Parallel LVTTL data input bit 2, latched by TCLK.
6 DIN3 input Parallel LVTTL data input bit 3, latched by TCLK.
7 DIN4 input Parallel LVTTL data input bit 4, latched by TCLK.
8 DIN5 input Parallel LVTTL data input bit 5, latched by TCLK.
9 DIN6 input Parallel LVTTL data input bit 6, latched by TCLK.
10 DIN7 input Parallel LVTTL data input bit 7, latched by TCLK.
11 DIN8 input Parallel LVTTL data input bit 8, latched by TCLK.
12 DIN9 input Parallel LVTTL data input bit 9, latched by TCLK.
13 TCLK_R/F input LVTTL logic input; low selects a TCLK falling-edge data strobe and high selects a TCLK rising-edge data strobe.
14 TCLK input LVTTL-level reference clock input accepting 10 MHz to 66 MHz; it strobes parallel data into the input latch and provides the PLL reference frequency.
15 DGND power_in Digital circuit ground.
16 DGND power_in Digital circuit ground.
17 AVCC power_in Analog circuit power supply for the PLL and analog circuits.
18 AGND power_in Analog circuit ground for the PLL and analog circuits.
19 DEN input LVTTL logic input; high enables the serial data output, and driving it low puts the LVDS output into the high-impedance state.
20 AGND power_in Analog circuit ground for the PLL and analog circuits.
21 DO- output Inverting LVDS differential serial data output.
22 DO+ output Noninverting LVDS differential serial data output.
23 AGND power_in Analog circuit ground for the PLL and analog circuits.
24 PWRDN input LVTTL logic input; driving it low turns off the PLL, places the outputs in high-impedance, and enters a low-power mode.
25 AGND power_in Analog circuit ground for the PLL and analog circuits.
26 AVCC power_in Analog circuit power supply for the PLL and analog circuits.
27 DVCC power_in Digital circuit power supply.
28 DVCC power_in Digital circuit power supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SSOP-28-208mil
Category Interface
Pins 28

CAD (KiCad official)

  • Symbol: SN65LV1023AMDBREP
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: sn65lv1023amdbrep-etched.step / sn65lv1023amdbrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lv1023amdbrep.step / sn65lv1023amdbrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 2c0fadd4093ca5b1, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF