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SM6512D1RL

SPS · MOSFETs · DFN-8-EP(6.1x5.2)

SM6512D1RL from SPS, in a DFN-8-EP(6.1x5.2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the N-channel MOSFET, tied with pins 2 and 3, carrying up to 150A continuous at TA=25°C.
2 S passive Source terminal of the N-channel MOSFET, tied with pins 1 and 3, carrying up to 150A continuous at TA=25°C.
3 S passive Source terminal of the N-channel MOSFET, tied with pins 1 and 2, carrying up to 150A continuous at TA=25°C.
4 G input Gate terminal, with maximum gate-source voltage of ±20V and a threshold of 1V min to 2V max at ID=250µA.
5 D passive Drain terminal, tied with pins 6, 7 and 8, rated for 30V drain-source voltage.
6 D passive Drain terminal, tied with pins 5, 7 and 8, rated for 30V drain-source voltage.
7 D passive Drain terminal, tied with pins 5, 6 and 8, rated for 30V drain-source voltage.
8 D passive Drain terminal, tied with pins 5, 6 and 7, rated for 30V drain-source voltage.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SPS
Package DFN-8-EP(6.1x5.2)
Category Transistors
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 30 V ID = -250uA, VGS = 0V 2
Zero Gate Voltage Drain Current IDSS 1 uA VDS=30V, VGS=0V 2
Gate-Body leakage current IGSS -100 100 nA VDS = 0V, VGS = ±20V 2
Gate Threshold Voltage VGS(th) 1 1.5 2 V VDS = VGS ID = 250µA 2
Static Drain-Source On-Resistance RDS(ON) 1.7 2.4 mΩ VGS=10V, ID=20A 2
Static Drain-Source On-Resistance RDS(ON) 2.6 3.4 mΩ VGS=4.5V, ID=20A 2
Forward Transconductance gFS 70 S VDS=5V, ID=20A 2
Diode Forward Voltage VSD 0.72 1 V IS=1A 2
Maximum Body-Diode Continuous Current IS 150 A 2
Input Capacitance Ciss 3430 4184 pF VGS=0V, VDS=15V, f=1MHz 2
Output Capacitance Coss 1327 1632 pF VGS=0V, VDS=15V, f=1MHz 2
Reverse Transfer Capacitance Crss 175 208 pF VGS=0V, VDS=15V, f=1MHz 2
Body Diode Reverse Recovery Time trr 22 ns IF=-8A, dI/dt=500A/µs 2
Body Diode Reverse Recovery Charge Qrr 58 nC IF=18A, dI/dt=500A/µs 2
Gate resistance Rg 5.15 Ω VGS=0V, VDS=0V, f=1MHz 2
Total Gate Charge (10V) Qg 25 nC VGS=10V, VDS=15V, ID=20A 2
Total Gate Charge (4.5V) Qg 12.5 nC VGS=10V, VDS=15V, ID=20A 2
Gate Source Charge Qgs 7.21 nC VGS=10V, VDS=15V, ID=20A 2
Gate Drain Charge Qgd 10.3 nC VGS=10V, VDS=15V, ID=20A 2
Turn-On Delay Time tD(on) 11 ns VGS=10V, VDS=15V, RL=0.75Ω, RGEN=3Ω 2
Turn-On Rise Time tr 8.8 ns VGS=10V, VDS=15V, RL=0.75Ω, RGEN=3Ω 2
Turn-Off Delay Time tD(off) 30.8 ns VGS=10V, VDS=15V, RL=0.75Ω, RGEN=3Ω 2
Turn-Off Fall Time tf 9.9 ns VGS=10V, VDS=15V, RL=0.75Ω, RGEN=3Ω 2
Drain-Source Voltage VDS 30 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 150 A TA=25°C 1
Continuous Drain Current ID 115 A TA=70°C 1
Pulsed Drain Current IDM 240 A 1
Avalanche Current IAR 48 A 1
Repetitive avalanche energy EAR 110.4 mJ L=0.1mH 1
Power Dissipation PD 83 W TA=25°C 1
Power Dissipation PD 33 W TA=70°C 1
Junction and Storage Temperature Range TJ, TSTG -55 150 °C 1
Maximum Junction-to-Ambient RθJA 6 9 °C/W t ≤ 10s 1
Maximum Junction-to-Ambient RθJA 12 14 °C/W Steady State 1
Maximum Junction-to-Lead RθJL 3 5 °C/W Steady State 1

CAD (KiCad official)

  • Symbol: SM6512D1RL
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN-8-EP(6.1x5.2) (KiCad packages3D, STEP)
  • 3D model files: sm6512d1rl-etched.step / sm6512d1rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sm6512d1rl.step / sm6512d1rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SPS datasheet (4 pp, sha256 6220dd99fb688a33, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF