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SLM6900

Public Made by Adom

by adom

SOLA IC Battery Management, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs slm6900: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json slm6900: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md slm6900: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
slm6900-etched.fit.json slm6900: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
slm6900-etched.glb slm6900: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
slm6900-etched.step slm6900: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
slm6900.glb Publish 0.1.0 · Ray
slm6900.kicad_mod Publish 0.1.0 · Ray
slm6900.kicad_sym Publish 0.1.0 · Ray
slm6900.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
slm6900.step Publish 0.1.0 · Ray

SLM6900

SOLA IC · Battery Management · TSSOP-14

SLM6900 from SOLA IC, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRV output External PMOS gate drive output. The voltage is clamped by GVC to VCC-6.3V (typ.), allowing a low-VGS PMOS to be used for improved efficiency and lower cost. Switches at the 300 kHz oscillator frequency.
2 PVCC power_in Gate driver supply input. Supplies the DRV output stage; tied to VCC in typical applications.
3 VCC power_in Chip supply input. Operating input supply range 6.8 V to 28 V (absolute max VIN 30 V continuous / 45 V inrush).
4 NCHRG output Open-drain charge status indicator (typically drives a red LED). Pulled low while charging is in progress (VNCHRG ~0.3 V typ at 5 mA), high-impedance otherwise. Pulses at 1-4 Hz when the battery is disconnected.
5 NSTDBY output Open-drain charge-done status indicator (typically drives a green LED). Pulled low when the battery is fully charged (VNSTDBY ~0.3 V typ at 5 mA), high-impedance otherwise.
6 NTC input Battery temperature detection input. Sources ~50 uA (45-55 uA) into an external NTC thermistor (10 kΩ @ 25°C typical) referenced to GND. Suspends charging outside the 190 mV low / 1.46 V high thresholds. Leave floating or tie to VCC to disable; tying to GND disables charging.
7 SEL input Battery output voltage select. Tie to GND for 3-cell mode (12.6 V float), tie to VCC for 4-cell mode (16.8 V float), or leave floating to use an external FB divider (VFB = 1.205 V reference).
8 COMP passive Loop stability compensation node. Connect a series R-C (e.g., 120 Ω / 220 nF) to GND close to the IC.
9 FB input Battery voltage feedback input. In SEL=GND/VCC modes an optional series resistor trims float voltage; when SEL is floating, FB regulates to 1.205 V and an external divider sets VFLOAT = 1.205 × (R4+R5)/R5.
10 ISN input Charge current sense negative input. Connect to the battery-side end of the current-sense resistor RS. In constant-current mode VS(ISP-ISN) = 120 mV; RS = 0.12/IBAT.
11 ISP input Charge current sense positive input. Connect to the inductor/output-side end of RS. Kelvin-connect ISP/ISN directly across RS for best accuracy.
12 GND power_in Small-signal (analog) ground. Return the COMP compensation capacitor here, close to the IC, to keep PGND switching noise off the control loop.
13 PGND power_in Power ground / gate-driver return. Carries the PMOS gate-drive switching current; connect to the ground plane close to the input capacitor.
14 GVC passive Gate voltage clamp node. A 100 nF capacitor from GVC to VCC clamps the external PMOS gate-drive swing to ≥VCC-6.3 V, protecting low-VGS PMOS parts.

Key specifications

Parameter Value
Manufacturer SOLA IC
Package TSSOP-14
Category PMIC
Pins 14

CAD (KiCad official)

  • Symbol: SLM6900
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: slm6900-etched.step / slm6900-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); slm6900.step / slm6900.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
slm6900.step 194 KB You want the bare part, or you mark your own boards.
slm6900-etched.step 2.2 MB You want the part with SLM6900 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 530 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SOLA IC datasheet (13 pp, sha256 636f021dcac3bc22, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF