component

SIT3232EEUE

Public Made by Adom

by adom

SIT RS232 ICs, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sit3232eeue: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sit3232eeue: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
README.md sit3232eeue: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sit3232eeue-etched.fit.json sit3232eeue: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sit3232eeue-etched.glb sit3232eeue: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
sit3232eeue-etched.step sit3232eeue: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray
sit3232eeue.glb Publish 0.1.0 · Ray
sit3232eeue.kicad_mod Publish 0.1.0 · Ray
sit3232eeue.kicad_sym Publish 0.1.0 · Ray
sit3232eeue.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sit3232eeue.step Publish 0.1.0 · Ray

SIT3232EEUE

SIT · RS232 ICs · TSSOP-16

SIT3232EEUE from SIT, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C1+ passive Positive terminal of the first charge-pump flying capacitor (C1). Connect a 1µF capacitor between C1+ and C1- to enable the voltage-doubler stage that generates V+.
2 V+ power_out Doubled positive supply output from the internal charge pump (approximately +2×VCC). Bypass to GND with a 1µF capacitor. Absolute max VCC-0.3 to +7V.
3 C1- passive Negative terminal of the first charge-pump flying capacitor (C1). Pairs with C1+ via a 1µF external capacitor.
4 C2+ passive Positive terminal of the second charge-pump flying capacitor (C2). Connect a 1µF capacitor between C2+ and C2- to enable the inverter stage that generates V-.
5 C2- passive Negative terminal of the second charge-pump flying capacitor (C2). Pairs with C2+ via a 1µF external capacitor.
6 V- power_out Inverted (negative) supply output from the internal charge pump (approximately -2×VCC). Bypass to GND with a 1µF capacitor. Absolute max +0.3 to -7V.
7 T2OUT output Second RS-232 transmitter output (driver 2). Drives the external RS-232 line at ±4 to ±5V into a 3kΩ load; ESD protected to ±15kV HBM / ±8kV IEC contact. Absolute max output swing ±13.2V.
8 R2IN input Second RS-232 receiver input (receiver 2). Accepts ±25V RS-232-level signals; input impedance 3-7kΩ typ 5kΩ; thresholds VRIL 0.6V min / VRIH 2.4V max at VCC=3.3V. ESD protected to ±15kV HBM.
9 R2OUT output Second receiver logic-level output (CMOS). Drives VCC-referenced logic: VOL ≤ 0.4V @ 1.6mA, VOH ≥ VCC-0.6V @ 0.5mA.
10 T2IN input Second transmitter logic input (CMOS/TTL). VIL ≤ 0.8V, VIH ≥ 2V, 0.3V typ hysteresis, input current ≤ ±1µA. Absolute max -0.3 to +6V.
11 T1IN input First transmitter logic input (CMOS/TTL). VIL ≤ 0.8V, VIH ≥ 2V, 0.3V typ hysteresis, input current ≤ ±1µA. Absolute max -0.3 to +6V.
12 R1OUT output First receiver logic-level output (CMOS). Drives VCC-referenced logic: VOL ≤ 0.4V @ 1.6mA, VOH ≥ VCC-0.6V @ 0.5mA.
13 R1IN input First RS-232 receiver input (receiver 1). Accepts ±25V RS-232-level signals; input impedance 3-7kΩ typ 5kΩ; thresholds VRIL 0.6V min / VRIH 2.4V max at VCC=3.3V. ESD protected to ±15kV HBM.
14 T1OUT output First RS-232 transmitter output (driver 1). Drives the external RS-232 line at ±4 to ±5V into a 3kΩ load; short-circuit current 60mA max; ESD protected to ±15kV HBM / ±8kV IEC contact.
15 GND power_in Ground reference for all signals and the charge pump.
16 VCC power_in Positive supply input, 3.0V to 5.5V (typ 3.3V). Bypass to GND with a 1µF capacitor. Absolute max -0.3 to +6V; typical supply current 2mA (no load).

Key specifications

Parameter Value
Manufacturer SIT
Package TSSOP-16
Category Interface
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • SIT3232EEUE

CAD (KiCad official)

  • Symbol: SIT3232EEUE
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sit3232eeue-etched.step / sit3232eeue-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sit3232eeue.step / sit3232eeue.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sit3232eeue.step 205 KB You want the bare part, or you mark your own boards.
sit3232eeue-etched.step 2.7 MB You want the part with SIT3232EEUE already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 668 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SIT datasheet (12 pp, sha256 2714c7267d52ec1d, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF