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SI8600AB-B-IS
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SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SI8600AB-B-IS
SILICON LABS · Digital Isolators · SOIC-8
SI8600AB-B-IS from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | Side A power supply terminal; connect to a source of 3.0 to 5.5 V. |
| 2 | ASDA | bidirectional | Side A data (open drain) input or output. |
| 3 | ASCL | bidirectional | Side A clock input or output; open drain I/O for Si8600. |
| 4 | AGND | power_in | Side A ground terminal. |
| 5 | BGND | power_in | Side B ground terminal. |
| 6 | BSCL | bidirectional | Side B clock input or output; open drain I/O for Si8600. |
| 7 | BSDA | bidirectional | Side B data (open drain) input or output. |
| 8 | BVDD | power_in | Side B power supply terminal; connect to a source of 3.0 to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | TA | -40 | 25 | 125 | °C | Footnote 1: max depends on data frequency, output loading, channel count and supply voltage | 13 |
| Supply Voltage (Side A) | AVDD | 3 | 5.5 | V | 13 | ||
| Supply Voltage (Side B) | BVDD | 3 | 5.5 | V | 13 | ||
| Si8600 AVDD Current | Idda | 5.4 | 7.6 | mA | All channels = 0 dc | 13 | |
| Si8600 BVDD Current | Iddb | 4.3 | 6.5 | mA | All channels = 0 dc | 13 | |
| Si8600 AVDD Current | Idda | 2.6 | 3.9 | mA | All channels = 1 dc | 13 | |
| Si8600 BVDD Current | Iddb | 1.9 | 2.9 | mA | All channels = 1 dc | 13 | |
| Si8600 AVDD Current | Idda | 3.3 | 5 | mA | All channels = 1.7 MHz | 13 | |
| Si8600 BVDD Current | Iddb | 2.6 | 3.9 | mA | All channels = 1.7 MHz | 13 | |
| Logic Input Threshold (Side A) | I2CVT (Side A) | 410 | 540 | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 | |
| Logic Low Output Voltage (Side A) | I2CVOL (Side A) | 540 | 800 | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 | |
| Input/Output Logic Low Level Difference (Side A) | I2CΔV (Side A) | 50 | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 | ||
| Logic High Input Voltage (Side B) | I2CVIH (Side B) | 2 | V | 14 | |||
| Logic Low Input Voltage (Side B) | I2CVIL (Side B) | 0.8 | V | 14 | |||
| Logic Low Output Voltage (Side B) | I2CVOL (Side B) | 500 | mV | ISCLB = 35 mA | 14 | ||
| SCL and SDA Logic High Leakage | Isdaa, Isdab, Iscla, Isclb | 2 | 10 | µA | SDAA, SCLA = VSSA; SDAB, SCLB = VSSB | 14 | |
| Maximum I2C Bus Frequency | Fmax | 1.7 | MHz | 15 | |||
| Propagation Delay 5 V Side A to Side B Rising | Tphab | 38 | 45 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Propagation Delay 5 V Side A to Side B Falling | Tplab | 15 | 26 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Propagation Delay 5 V Side B to Side A Rising | Tphba | 33 | 46 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Propagation Delay 5 V Side B to Side A Falling | Tplba | 11 | 22 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Propagation Delay 3.3 V Side A to Side B Rising | Tphab | 44 | 55 | ns | R1 = 806, R2 = 499 | 15 | |
| Propagation Delay 3.3 V Side A to Side B Falling | Tplab | 17 | 29 | ns | R1 = 806, R2 = 499 | 15 | |
| Propagation Delay 3.3 V Side B to Side A Rising | Tphba | 30 | 40 | ns | R1 = 806, R2 = 499 | 15 | |
| Propagation Delay 3.3 V Side B to Side A Falling | Tplba | 14 | 27 | ns | R1 = 806, R2 = 499 | 15 | |
| Pulse Width Distortion 5 V Side A Low to Side B Low | PWDAB | 22 | 32 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Pulse Width Distortion 5 V Side B Low to Side A Low | PWDBA | 21 | 32 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 | |
| Pulse Width Distortion 3.3 V Side A Low to Side B Low | PWDAB | 27 | 35 | ns | R1 = 806, R2 = 499 | 15 | |
| Pulse Width Distortion 3.3 V Side B Low to Side A Low | PWDBA | 15 | 25 | ns | R1 = 806, R2 = 499 | 15 | |
| VDD Undervoltage Threshold (rising) | VDDUV+ | 1.95 | 2.24 | 2.375 | V | VDD1, VDD2 rising | 17 |
| VDD Undervoltage Threshold (falling) | VDDUV- | 1.88 | 2.16 | 2.325 | V | VDD1, VDD2 falling | 17 |
| VDD Undervoltage Hysteresis | VDDHYS | 50 | 70 | 95 | mV | 17 | |
| Common Mode Transient Immunity | CMTI | 35 | 50 | kV/µs | VI = VDD or 0 V; VCM = 1500 V | 17 | |
| Start-up Time | tSTART | 15 | 40 | µs | Time from application of power to valid data at the output | 17 | |
| Storage Temperature | TSTG | -65 | 150 | ºC | 22 | ||
| Ambient Temperature Under Bias | TA | -40 | 125 | ºC | 22 | ||
| Junction Temperature | TJ | 150 | °C | 22 | |||
| Supply Voltage | VDD | -0.5 | 7 | V | 22 | ||
| Input Voltage | VI | -0.5 | V | Printed maximum is VDD + 0.5 V | 22 | ||
| Output Voltage | VO | -0.5 | V | Printed maximum is VDD + 0.5 V | 22 | ||
| Output Current Drive (non-I2C channels) | IO | -10 | 10 | mA | 22 | ||
| Side A output current drive (I2C channels) | IO | -15 | 15 | mA | 22 | ||
| Side B output current drive (I2C channels) | IO | -75 | 75 | mA | 22 | ||
| Lead Solder Temperature | 260 | ºC | 10 s | 22 | |||
| Maximum Isolation (Input to Output), NB SOIC-8 | 4500 | VRMS | 1 sec | 22 | |||
| Case Temperature (safety limiting) | TS | 150 | °C | IEC safety limiting value, NB SOIC-8 | 20 | ||
| Safety Input Current (NB SOIC-8) | IS | 160 | mA | θJA = 140 °C/W (NB SOIC-8); AVDD, BVDD = 5.5 V, TJ = 150 °C, TA = 25 °C | 20 | ||
| Device Power Dissipation (safety limiting, NB SOIC-8) | PD | 220 | mW | 20 | |||
| IC Junction-to-Air Thermal Resistance (NB SOIC-8) | θJA | 140 | °C/W | 21 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | 13.3 Top Marking: 16-Pin Narrow Body SOIC .....................36 silabs.com / Building a more connected world. Rev. 1.72 / 3 | 3 |
CAD (KiCad official)
- Symbol:
SI8600AB-B-IS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
si8600ab-b-is-etched.step/si8600ab-b-is-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si8600ab-b-is.step/si8600ab-b-is.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (39 pp, sha256
1a5d29d7cad4bb14, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SI8600AB-B-IS
**SILICON LABS** · Digital Isolators · SOIC-8
SI8600AB-B-IS from SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | Side A power supply terminal; connect to a source of 3.0 to 5.5 V. |
| 2 | ASDA | bidirectional | Side A data (open drain) input or output. |
| 3 | ASCL | bidirectional | Side A clock input or output; open drain I/O for Si8600. |
| 4 | AGND | power_in | Side A ground terminal. |
| 5 | BGND | power_in | Side B ground terminal. |
| 6 | BSCL | bidirectional | Side B clock input or output; open drain I/O for Si8600. |
| 7 | BSDA | bidirectional | Side B data (open drain) input or output. |
| 8 | BVDD | power_in | Side B power supply terminal; connect to a source of 3.0 to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | TA | -40 | 25 | 125 | °C | Footnote 1: max depends on data frequency, output loading, channel count and supply voltage | 13 |
| Supply Voltage (Side A) | AVDD | 3 | | 5.5 | V | | 13 |
| Supply Voltage (Side B) | BVDD | 3 | | 5.5 | V | | 13 |
| Si8600 AVDD Current | Idda | | 5.4 | 7.6 | mA | All channels = 0 dc | 13 |
| Si8600 BVDD Current | Iddb | | 4.3 | 6.5 | mA | All channels = 0 dc | 13 |
| Si8600 AVDD Current | Idda | | 2.6 | 3.9 | mA | All channels = 1 dc | 13 |
| Si8600 BVDD Current | Iddb | | 1.9 | 2.9 | mA | All channels = 1 dc | 13 |
| Si8600 AVDD Current | Idda | | 3.3 | 5 | mA | All channels = 1.7 MHz | 13 |
| Si8600 BVDD Current | Iddb | | 2.6 | 3.9 | mA | All channels = 1.7 MHz | 13 |
| Logic Input Threshold (Side A) | I2CVT (Side A) | 410 | | 540 | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 |
| Logic Low Output Voltage (Side A) | I2CVOL (Side A) | 540 | | 800 | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 |
| Input/Output Logic Low Level Difference (Side A) | I2CΔV (Side A) | 50 | | | mV | ISDAA, ISCLA (>0.5 mA, <3.0 mA) | 14 |
| Logic High Input Voltage (Side B) | I2CVIH (Side B) | 2 | | | V | | 14 |
| Logic Low Input Voltage (Side B) | I2CVIL (Side B) | | | 0.8 | V | | 14 |
| Logic Low Output Voltage (Side B) | I2CVOL (Side B) | | | 500 | mV | ISCLB = 35 mA | 14 |
| SCL and SDA Logic High Leakage | Isdaa, Isdab, Iscla, Isclb | | 2 | 10 | µA | SDAA, SCLA = VSSA; SDAB, SCLB = VSSB | 14 |
| Maximum I2C Bus Frequency | Fmax | | | 1.7 | MHz | | 15 |
| Propagation Delay 5 V Side A to Side B Rising | Tphab | | 38 | 45 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Propagation Delay 5 V Side A to Side B Falling | Tplab | | 15 | 26 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Propagation Delay 5 V Side B to Side A Rising | Tphba | | 33 | 46 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Propagation Delay 5 V Side B to Side A Falling | Tplba | | 11 | 22 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Propagation Delay 3.3 V Side A to Side B Rising | Tphab | | 44 | 55 | ns | R1 = 806, R2 = 499 | 15 |
| Propagation Delay 3.3 V Side A to Side B Falling | Tplab | | 17 | 29 | ns | R1 = 806, R2 = 499 | 15 |
| Propagation Delay 3.3 V Side B to Side A Rising | Tphba | | 30 | 40 | ns | R1 = 806, R2 = 499 | 15 |
| Propagation Delay 3.3 V Side B to Side A Falling | Tplba | | 14 | 27 | ns | R1 = 806, R2 = 499 | 15 |
| Pulse Width Distortion 5 V Side A Low to Side B Low | PWDAB | | 22 | 32 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Pulse Width Distortion 5 V Side B Low to Side A Low | PWDBA | | 21 | 32 | ns | No bus capacitance, R1 = 1400, R2 = 499 | 15 |
| Pulse Width Distortion 3.3 V Side A Low to Side B Low | PWDAB | | 27 | 35 | ns | R1 = 806, R2 = 499 | 15 |
| Pulse Width Distortion 3.3 V Side B Low to Side A Low | PWDBA | | 15 | 25 | ns | R1 = 806, R2 = 499 | 15 |
| VDD Undervoltage Threshold (rising) | VDDUV+ | 1.95 | 2.24 | 2.375 | V | VDD1, VDD2 rising | 17 |
| VDD Undervoltage Threshold (falling) | VDDUV- | 1.88 | 2.16 | 2.325 | V | VDD1, VDD2 falling | 17 |
| VDD Undervoltage Hysteresis | VDDHYS | 50 | 70 | 95 | mV | | 17 |
| Common Mode Transient Immunity | CMTI | 35 | 50 | | kV/µs | VI = VDD or 0 V; VCM = 1500 V | 17 |
| Start-up Time | tSTART | | 15 | 40 | µs | Time from application of power to valid data at the output | 17 |
| Storage Temperature | TSTG | -65 | | 150 | ºC | | 22 |
| Ambient Temperature Under Bias | TA | -40 | | 125 | ºC | | 22 |
| Junction Temperature | TJ | | | 150 | °C | | 22 |
| Supply Voltage | VDD | -0.5 | | 7 | V | | 22 |
| Input Voltage | VI | -0.5 | | | V | Printed maximum is VDD + 0.5 V | 22 |
| Output Voltage | VO | -0.5 | | | V | Printed maximum is VDD + 0.5 V | 22 |
| Output Current Drive (non-I2C channels) | IO | -10 | | 10 | mA | | 22 |
| Side A output current drive (I2C channels) | IO | -15 | | 15 | mA | | 22 |
| Side B output current drive (I2C channels) | IO | -75 | | 75 | mA | | 22 |
| Lead Solder Temperature | | | | 260 | ºC | 10 s | 22 |
| Maximum Isolation (Input to Output), NB SOIC-8 | | | | 4500 | VRMS | 1 sec | 22 |
| Case Temperature (safety limiting) | TS | | | 150 | °C | IEC safety limiting value, NB SOIC-8 | 20 |
| Safety Input Current (NB SOIC-8) | IS | | | 160 | mA | θJA = 140 °C/W (NB SOIC-8); AVDD, BVDD = 5.5 V, TJ = 150 °C, TA = 25 °C | 20 |
| Device Power Dissipation (safety limiting, NB SOIC-8) | PD | | | 220 | mW | | 20 |
| IC Junction-to-Air Thermal Resistance (NB SOIC-8) | θJA | | 140 | | °C/W | | 21 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | | 13.3 Top Marking: 16-Pin Narrow Body SOIC .....................36 silabs.com / Building a more connected world. Rev. 1.72 / 3 | 3 |
## CAD (KiCad official)
- Symbol: `SI8600AB-B-IS`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `si8600ab-b-is-etched.step` / `si8600ab-b-is-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `si8600ab-b-is.step` / `si8600ab-b-is.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [SILICON LABS datasheet](docs/si8600ab-b-is-datasheet.pdf) (39 pp, sha256 `1a5d29d7cad4bb14`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/si8600ab-b-is-datasheet.pdf)