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SI8261BCC-C-ISR
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SKYWORKS SILICON LABS Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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SI8261BCC-C-ISR
SKYWORKS SILICON LABS · Digital Isolators · SOIC-8
SI8261BCC-C-ISR from SKYWORKS SILICON LABS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect; these pins are not internally connected, and should be tied to the ground plane to maximize CMTI performance. |
| 2 | ANODE | input | Anode of the LED emulator; VO follows the signal applied to this input with respect to the CATHODE input. |
| 3 | CATHODE | input | Cathode of the LED emulator; VO follows the signal applied to ANODE with respect to this input. |
| 4 | NC | unconnected | No connect; this pin is not internally connected, and should be tied to the ground plane to maximize CMTI performance. |
| 5 | GND | power_in | External MOSFET source connection and ground reference for VDD; typically connected to ground but may be tied to a negative or positive voltage. |
| 6 | VO | output | Output signal; both VO pins (6 and 7) are required to be shorted together for 4.0 A compliance. |
| 7 | VO | output | Output signal; both VO pins (6 and 7) are required to be shorted together for 4.0 A compliance. |
| 8 | VDD | power_in | Output-side power supply input referenced to GND, 30 V max (recommended operating supply is 6.5 to 30 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS SILICON LABS |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 6.5 | 30 | V | 4 | ||
| Input Current | IF(ON) | 6 | 30 | mA | see Figure 1 | 4 | |
| Operating Temperature (Ambient) | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage (VDD, GND) | VDD | 6.5 | 30 | V | 4 | ||
| Supply Current (Output High) | IDD | 1.8 | 2.4 | mA | IF = 10 mA, VDD = 15 V | 4 | |
| Supply Current (Output High) | IDD | 2 | 2.7 | mA | IF = 10 mA, VDD = 30 V | 4 | |
| Supply Current (Output Low) | IDD | 1.5 | 2.1 | mA | VF = 0 V; IF = 0 mA, VDD = 15 V | 4 | |
| Supply Current (Output Low) | IDD | 1.7 | 2.4 | mA | VF = 0 V; IF = 0 mA, VDD = 30 V | 4 | |
| Input Current Threshold | IF(TH) | 3.6 | mA | 4 | |||
| Input Forward Voltage (OFF) | VF(OFF) | 1 | V | Measured at ANODE with respect to CATHODE. | 4 | ||
| Input Forward Voltage (ON) | VF(ON) | 1.6 | 2.8 | V | Measured at ANODE with respect to CATHODE. | 4 | |
| Output Resistance High (Source) | ROH | 2.6 | 5.1 | Ω | Si826xBxx devices (IOH = -1 A) | 4 | |
| Output Resistance Low (Sink) | ROL | 0.8 | 2 | Ω | Si826xBxx devices (IOL = 2 A) | 4 | |
| Output High Current (Source) | IOH | 0.5 | 1.8 | A | Si826xBxx devices (IF = 0), (tPW_IOH < 250 ns), (VDD -VO = 7.5 V) | 5 | |
| Output Low Current (Sink) | IOL | 1.2 | 4 | A | Si826xBxx devices (IF = 10 mA), (tPW_IOL < 250 ns), (VO - GND = 4.2 V) | 5 | |
| High-Level Output Voltage (VDD-referenced offset) | VOH | -0.5 | -0.25 | V (relative to VDD) | Si826xBxx devices (IOUT = -100 mA); printed as VDD-0.5 (min) and VDD-0.25 (typ) | 5 | |
| Low-Level Output Voltage | VOL | 80 | 200 | mV | Si826xBxx devices (IOUT = 100 mA), (IF = 10 mA) | 5 | |
| UVLO Threshold + (Si826xxCx mode) | VDDUV+ | 10.5 | 12 | 13.5 | V | VDD rising; see Figure 13 | 6 |
| UVLO Threshold, (Si826xxCx mode) | VDDUV- | 9.4 | 10.7 | 12.2 | V | VDD falling; see Figure 13 | 6 |
| Input noise filter cut-off pulse width | tNFC | 15 | ns | 6 | |||
| Propagation delay (Low-to-High) | tPLH | 20 | 40 | 60 | ns | CL = 200 pF | 6 |
| Propagation delay (High-to-Low) | tPHL | 10 | 30 | 50 | ns | CL = 200 pF | 6 |
| Pulse Width Distortion | PWD | 17 | 28 | ns | /tPLH -tPHL/ | 6 | |
| Propagation Delay Difference | PDD | -1 | 25 | ns | tPHLMAX -tPLHMIN | 6 | |
| Rise time | tR | 5.5 | 15 | ns | CL = 200 pF | 6 | |
| Fall time | tF | 8.5 | 20 | ns | CL = 200 pF | 6 | |
| Device Startup Time | tSTART | 16 | 30 | µs | 6 | ||
| Common Mode Transient Immunity | CMTI | 35 | 50 | kV/µs | Output = low or high (VCM = 1500 V), (IF > 6 mA) (See Figure 4) | 6 | |
| Storage Temperature | TSTG | -65 | 150 | °C | 13 | ||
| Operating Temperature | TA | -40 | 125 | °C | 13 | ||
| Junction Temperature | TJ | 140 | °C | 13 | |||
| Average Forward Input Current | IF(AVG) | 30 | mA | 13 | |||
| Peak Transient Input Current | IFTR | 1 | A | < 1 µs pulse width, 300 ps | 13 | ||
| Reverse Input Voltage | VR | 0.3 | V | 13 | |||
| Supply Voltage (absolute) | VDD | -0.5 | 36 | V | 13 | ||
| Output Voltage | VOUT | -0.5 | 36 | V | 13 | ||
| Peak Output Current (4.0 Amp versions) | IOPK | 4 | A | tPW = 10 µs, duty cycle = 0.2% | 13 | ||
| Input Power Dissipation | PI | 75 | mW | 13 | |||
| Output Power Dissipation | PO | 225 | mW | 13 | |||
| Total Power Dissipation | PT | 300 | mW | all packages limited by thermal derating curve | 13 | ||
| Lead Solder Temperature | 260 | °C | 10 s | 13 | |||
| HBM Rating ESD | ESD | 4 | kV | 13 | |||
| Machine Model ESD | ESD | 300 | V | 13 | |||
| CDM ESD | CDM | 2000 | V | 13 | |||
| Maximum Isolation Voltage (1 s) SOIC-8 | 4500 | VRMS | 1 s, SOIC-8 column | 13 | |||
| IC Junction-to-Air Thermal Resistance (SOIC-8) | JA | 110 | °C/W | SOIC-8 column | 11 | ||
| UVLO lockout hysteresis (Si826xxCx mode) | VDDHYS | 1.3 | V | 6 | |||
| Input Current Hysteresis | IHYS | 0.34 | mA | 4 | |||
| Input Capacitance | CI | 15 | pF | f = 100 kHz, VF = 0 V | 4 | ||
| Minimum pulse width | tPMIN | 30 | ns | 6 | |||
| High-Level Output Voltage (VDD-referenced offset) | VOH | 0 | V (relative to VDD) | Si826xBxx devices (IOUT = 0 mA), (IF = 0 mA); printed as VDD | 5 |
CAD (KiCad official)
- Symbol:
SI8261BCC-C-ISR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
si8261bcc-c-isr-etched.step/si8261bcc-c-isr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si8261bcc-c-isr.step/si8261bcc-c-isr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS SILICON LABS datasheet (40 pp, sha256
0b10b67ed5aa18f6, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).