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SI7960DP-VB

Public Made by Adom

by adom

VBsemi Elec MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI7960DP-VB

VBsemi Elec · MOSFETs · DFN5x6-8

SI7960DP-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of N-channel MOSFET 1 (60 V VDS rating).
2 G1 input Gate of N-channel MOSFET 1 (VGS maximum ±20 V).
3 S2 passive Source of N-channel MOSFET 2 (60 V VDS rating).
4 G2 input Gate of N-channel MOSFET 2 (VGS maximum ±20 V).
5 D2 passive Drain of N-channel MOSFET 2, internally common with pins 5 and 6 (60 V VDS rating).
6 D2 passive Drain of N-channel MOSFET 2, internally common with pins 5 and 6 (60 V VDS rating).
7 D1 passive Drain of N-channel MOSFET 1, internally common with pins 7 and 8 (60 V VDS rating).
8 D1 passive Drain of N-channel MOSFET 1, internally common with pins 7 and 8 (60 V VDS rating).
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package DFN5x6-8
Category Transistors/Thyristors
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS 60 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID 17 A TJ = 150 °C, TC = 25 °C 1
Continuous drain current ID 8 A TA = 25 °C (note a) 1
Pulsed drain current IDM 40 A 1
Source-drain diode current IS 19 A TC = 25 °C 1
Source-drain diode current IS 3 A TA = 25 °C (notes b, c) 1
Maximum power dissipation PD 22 W TC = 25 °C 1
Maximum power dissipation PD 14 W TC = 70 °C 1
Maximum power dissipation PD 3.6 W TA = 25 °C (notes b, c) 1
Maximum power dissipation PD 2.3 W TA = 70 °C (notes b, c) 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Soldering recommendations (peak temperature) 260 °C notes d, e 1
Maximum junction-to-ambient RthJA 26 35 °C/W t = 10 s (notes b, f) 1
Maximum junction-to-ambient RthJA 80 °C/W steady state (note f) 1
Maximum junction-to-case (drain) RthJC 45.5 °C/W steady state 1
Drain-source breakdown voltage VDS 60 V VGS = 0 V, ID = 250 μA 2
Gate threshold voltage VGS(th) 1.2 2.7 V VDS = VGS, ID = 250 μA 2
Gate-body leakage IGSS 100 nA VDS = 0 V, VGS = ±20 V 2
Zero gate voltage drain current IDSS 1 μA VDS = 60 V, VGS = 0 V 2
Zero gate voltage drain current IDSS 10 μA VDS = 60 V, VGS = 0 V, TJ = 85 °C 2
On-state drain current ID(on) 60 A VDS ≥ 5 V, VGS = 10 V 2
Gate resistance Rg 0.12 0.6 1.2 Ω f = 1 MHz 2
Total gate charge Qg 15.2 23 nC VDS = 30 V, VGS = 10 V, ID = 11 A 2
Turn-on delay time td(on) 15 120 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Rise time tr 80 30 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Turn-off delay time td(off) 15 30 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Fall time tf 15 30 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 4.5 V, Rg = 1 Ω 2
Turn-on delay time td(on) 10 15 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 10 V, Rg = 1 Ω 2
Rise time tr 25 40 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 20 30 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 10 V, Rg = 1 Ω 2
Fall time tf 10 15 ns VDD = 30 V, RL = 3.45 Ω, ID 8.7 A, VGEN = 10 V, Rg = 1 Ω 2
Continuous source-drain diode current IS 8 A TC = 25 °C 2
Pulse diode forward current ISM 40 A 2
Body diode voltage VSD 0.8 1.2 V IS = 8.7 A 2
Body diode reverse recovery charge Qrr 30 45 nC IF = 8.7 A, di/dt = 100 A/μs, TJ = 25 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper d. The DFN 5x6 package is a leadless package. The end of the lead terminal is exposed copper 1

CAD (KiCad official)

  • Symbol: SI7960DP-VB
  • Footprint: Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm
  • 3D model: DFN5x6-8 (KiCad packages3D, STEP)
  • 3D model files: si7960dp-vb-etched.step / si7960dp-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si7960dp-vb.step / si7960dp-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (7 pp, sha256 071f74a7cc2c2dc1, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF